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You will automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Develop and validate DRC, LVS, and Fill runsets for the Synopsys IC Validator tool</li>\n<li>Collaborate with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes</li>\n<li>Automate qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python</li>\n<li>Troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges</li>\n<li>Interface directly with customers and FAEs to gather requirements, provide technical support, and ensure successful deployment of PV solutions</li>\n<li>Mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Accelerate the adoption and success of Synopsys IC Validator among leading semiconductor foundries and design houses</li>\n<li>Ensure robust and reliable PV runsets, enabling customers to achieve first-pass silicon success and reduce time-to-market</li>\n<li>Drive continuous improvement in automation and process efficiency, reducing manual intervention and error-prone steps</li>\n<li>Enhance customer satisfaction by providing timely and expert solutions to complex verification challenges</li>\n<li>Contribute to the development of next-generation verification methodologies and best practices within Synopsys</li>\n<li>Strengthen Synopsys&#39; reputation as a trusted partner in the global EDA ecosystem through technical excellence and customer-centric support</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>B.Tech, M.Tech, or MS in Electronics, VLSI, or a related field</li>\n<li>5-8 years of hands-on experience in the Physical Verification (PV) domain</li>\n<li>Advanced proficiency with EDA tools such as IC Validator, Calibre, Pegasus, and PVS</li>\n<li>Strong scripting skills in Perl, Tcl, and Python for automation and rule deck development</li>\n<li>Deep understanding of CMOS layout, ASIC design flows, and foundry process requirements</li>\n<li>Experience in writing and debugging DRC, LVS, ERC, and DFM rule decks</li>\n<li>Exposure to competitive EDA tools and awareness of their strengths and limitations</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>An analytical thinker with strong problem-solving abilities and meticulous attention to detail</li>\n<li>A collaborative team player who fosters knowledge sharing and mentorship</li>\n<li>Effective communicator, capable of translating technical concepts to diverse audiences</li>\n<li>Adaptable and proactive, with a passion for continuous learning and innovation</li>\n<li>Customer-focused, with a commitment to delivering high-quality solutions on time</li>\n<li>Self-driven, organized, and able to manage multiple priorities in a fast-paced environment</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:\nYou are an experienced and passionate engineer with a strong foundation in Electronics or VLSI, eager to work at the forefront of semiconductor technology. With 5-8 years of industry experience—primarily in Physical Verification (PV)—you thrive on solving complex layout and verification challenges for advanced process nodes. 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