The Air and Ground Deterrence (AGD) Division develops integrated robotic systems designed to provide multi-domain situational awareness and force protection across land, sea, and air. The Sentry Hardware team with AGD serves as the key system integrator of the Anduril Sentry Family of Systems (FoS).

We are looking for an Electrical Engineer to join our rapidly growing team in Irvine, CA. This role will own rapidly developed, ruggedized electronics design in addition to scaling legacy design concepts to support full-rate production. In this role, you will partner with our Architecture and Product Management team to help drive system requirements prior to owning full PCB and/or electrical system design.

Key Responsibilities:

• Take ownership as the main point of contact for electrical integration activities.
• Provide hands-on and in-field support of prototype and production-level product.
• Collaborate with mechanical engineers to optimize selection, design, and integration of high-power components, modules, and distribution.
• Trade-off component and module selections against size, weight, power, and EMC requirements.
• Collaborate with design team to achieve reliability goals at a system level in context of concepts of operation.

Requirements:

• Minimum 5 years of professional experience.
• Self-starter with the ability to design digital & analog electronics from concept and functional prototype, to production-ready product.
• Ability to troubleshoot existing hardware to find root cause of issues and implement improvements to improve the design.
• Develop clear documentation to capture design requirements, specifications, test coverage, and test reports.
• Complete full-cycle PCB design including collecting requirements, schematic design, component selection, completion of layout, bring-up, test, debug, validation, characterization, and integration with the system.
• Work closely with other mechanical, software, firmware, and test engineers to deliver fully functional products.
• Work in a fast-paced environment supporting new developments, active deployments, and customer-operated hardware.
• Concurrently manage involvement in multiple projects at various stages.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred Qualifications:

• Bachelor's Degree in Electrical Engineering or equivalent.
• 5+ years of experience designing, testing, and troubleshooting complex board designs and products.
• Competence with test equipment such as oscilloscopes, logic analyzers, thermal chambers, current-probes, and automation of tests.
• Familiarity with switch-mode power supply design and testing.
• Familiarity with standard interfaces such as Ethernet, CAN, I2C, SPI, PCIe, USB, etc.
• Familiarity with common MCU, CPU, FPGA devices and technologies.
• Knowledge of modern analog and digital electronics and electronic circuits.
• Exceptional organization and communication skills (both written and oral).
• Proficient with Altium Designer or equivalent electronic design automation design tools.
• Proficiency with scripting languages (Python, Matlab, etc.).
• Ability to root-cause full-stack HLOS application to hardware component-level issues.

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In this role, you will work closely with an interdisciplinary technical team to route high-speed mixed-signal designs, interact with fabricators and assemblers, and manage signal integrity in complex PCBs.

Key responsibilities include:

• Working directly with engineers to produce printed circuit board designs supporting Anduril's products.
• Applying modern design standards and guidelines to create high-reliability, highly manufacturable assemblies.
• Implementing combinations of high-speed digital, precision analog, RF, and high-power designs.
• Leading the team in establishing internal guidelines for design for manufacturing (DFM), design for assembly (DFA), and overall quality fabrication and assembly outputs.
• Developing and refining team processes for PCB design, part creation, and library/database standards.
• Coordinating external PCB design resources during design surges.

Required qualifications include:

• A bachelor's degree in electrical engineering or similar and 5+ years of professional experience in PCB design OR 10+ years of professional experience in PCB design.
• Ability to read and interpret schematics and apply best practices appropriate for each design.
• Expertise in applying relevant IPC standards, CID, CID+ certification.
• Expertise in PCB fabrication processes, limitations, design rules, and best practice.
• Experience using Altium Designer CAD tools (Allegro is a plus).
• Experience with developing component libraries and library management.
• Excellent communication skills with multiple fab houses (ensuring boards are built to print).
• Excellent communication skills with multiple assembly houses (ensuring boards are built to BOM).
• Experience with a variety of board types, including high density and high layer count (greater than 16) digital designs, power electronics, flex circuits, and RF circuits.
• Experience with HDI (high density interconnect) and thicker boards (greater than 1.6mm).
• Experience with high speed digital interfaces and controlled impedance routing requirements like USB, PCIe, Ethernet, SERDES, and DDR memory.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred qualifications include:

• Familiarity with RF board design.
• Experience with high-pin count packages (FPGA fanout).
• Familiarity with basic signal and power integrity rules (how they affect layout).

US Salary Range $111,000-$147,000 USD

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as DDR, PCIe/CXL, UCIe, AMBA and its applications. You can define and executing a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

What You’ll Be Doing:

Defining and developing ASIC RTL design and verification at both chip and block levels. Creating and executing design plans for complex digital designs, particularly focusing on DDR, PCIe,CXL,UAL, UCIe IO protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced design and verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have:

Enhancing the reliability and performance of Synopsys’ digital design processes. Driving innovations in DDR, PCIe, UAL, UCIe technology, contributing to the development of cutting-edge semiconductor solutions. Improving time-to-market for high-performance silicon chips through efficient methodologies. Building and nurturing a highly skilled development team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys’ capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You’ll Need:

Extensive experience in ASIC RTL design. In-depth knowledge of DDR, PCIe, UAL, UCIe and similar IO protocols and their applications. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams.

Who You Are:

A visionary leader with a strategic mindset. A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.

You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.

What You’ll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

A peek inside our office

Benefits: At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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The role involves leading the complete subsystem lifecycle,from requirements gathering and architecture definition to final release phases. This includes crafting subsystem architectures, developing comprehensive functional specifications, defining and implementing micro-architectures, and driving RTL quality checks.

The ideal candidate will have a minimum of 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects. They should be proficient with standard protocols including PCIe, DDR, UFS, USB, and AMBA, and have demonstrated expertise in low power design methodologies and DFT architecture.

As a leader, the candidate will inspire and guide their peers, leveraging their experience to drive innovation, efficiency, and reliability. They should be committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions.

The role offers a comprehensive range of health, wellness, and financial benefits to cater to the needs of the employee. The total rewards include both monetary and non-monetary offerings.

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As a Sr. Staff Engineer, you will be a key member of our Emulation/Validation team, responsible for bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.

Key responsibilities include:

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

The impact you will have includes enhancing cross-functional collaboration to elevate product quality and end-customer satisfaction, transforming the approach to Emulation IP usage in validating cutting-edge digital designs and system architectures, and driving innovation by defining and refining requirements for IP product development, particularly in emulation contexts.

To succeed in this role, you will need 8+ years of relevant experience in emulation, verification, or IP product development, expert-level knowledge of PCIe/ DDR/ Ethernet interfaces, including protocol and verification strategies, extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification, and a demonstrated track record in leading IP product development initiatives with a focus on emulation.

If you are a proactive and collaborative problem-solver with a passion for excellence, innovative thinker who embraces change and seeks out opportunities for continuous improvement, strong communicator able to articulate complex technical concepts to diverse audiences, resilient and adaptable, thriving in dynamic environments and embracing new challenges, and committed to mentoring others and fostering an inclusive, team-oriented culture, then we encourage you to apply for this exciting opportunity.

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Designing, developing, and maintaining Speed Adapter solutions for advanced protocols, including PCIe and CXL. Implementing protocol functionality on FPGA-based platforms to bridge real-world I/O with DUTs running at reduced speeds on emulation and prototyping systems. Collaborating with IP, emulation, and prototyping teams to deliver comprehensive, end-to-end system-level validation solutions. Developing and debugging RTL, firmware, and system-level components for Speed Adapter products. Supporting seamless integration with ZeBu and HAPS platforms, including creating example designs and reference flows. Participating in customer escalations, conducting root-cause analysis, and delivering solutions for complex system-level issues. Contributing to roadmap planning, feature definition, and technical differentiation versus competitive solutions.

Enable customers to connect pre-silicon designs to real devices, testers, and hosts with unmatched fidelity and performance. Advance industry-leading system-level validation technology for top semiconductor and hyperscale customers. Shape the adoption and implementation of next-generation protocols such as PCIe Gen6/Gen7 and CXL3.x/4.0. Drive innovation in hardware-assisted verification, influencing patent-pending technologies that differentiate Synopsys solutions. Enhance integration across IP, emulation, prototyping, and real-world connectivity to deliver robust validation platforms. Support global teams and customers, fostering technical excellence and collaborative problem-solving.

12 years+ relevant experience Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. Strong hands-on experience with PCIe and/or CXL protocols, including implementation and debugging. Solid understanding of digital design, RTL development, and FPGA-based systems. Experience with system-level validation, emulation, or prototyping environments. Familiarity with high-speed serial interfaces and real-world I/O connectivity. Strong debugging skills across RTL, firmware, and hardware/software boundaries. Ability to work effectively in a cross-geography, cross-functional team.

Innovative thinker with a strategic mindset. Collaborative team player who values diverse perspectives. Excellent communicator and technical mentor. Resilient problem-solver, able to navigate ambiguity and complexity. Customer-focused, with a commitment to delivering high-impact solutions. Adaptable and proactive, eager to stay ahead in a fast-evolving technology landscape.

You'll join the Speed Adapter engineering team within Synopsys' HW-Assisted Verification (HAV) organization. This talented group is dedicated to developing and deploying industry-leading Speed Adapter solutions that bridge advanced protocols and real-world interfaces with ZeBu emulation and HAPS prototyping platforms. The team collaborates globally across IP, emulation, and prototyping domains to deliver robust, high-performance system validation solutions, directly impacting the success of top semiconductor and hyperscale customers.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

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At Synopsys, interns dive into real-world projects, gaining hands-on experience while collaborating with our passionate teams worldwide,and having fun in the process! You'll have the freedom to share your ideas, unleash your creativity, and explore your interests. This is your opportunity to bring your solutions to life and work with cutting-edge technology that shapes not only the future of innovation but also your own career path.

Internship Experience:

• Plan and execute system-level testing for PCIe6 and PCIe7 protocols, focusing on reproducing and debugging customer issues with SNPS PHY.
• Develop and maintain Python-based test scripts to automate validation processes.
• Utilize lab instrumentation to conduct hands-on experiments and gather critical data.
• Collaborate with engineering teams to report findings, discuss next steps, and contribute to solutions that directly impact customer satisfaction.
• Engage in creative problem-solving, proactively seeking new approaches to resolve complex technical challenges.

What You'll Need:

• Currently pursuing a master’s degree in Electronic Engineering, Computer Science, or a related field.
• Strong programming skills in Python,ability to develop and troubleshoot test automation scripts is essential.
• Previous experience with lab instrumentation and hands-on testing environments, is a plus.
• Familiarity with high-speed SerDes protocols such as PCIe.
• Proactive and persistent approach to problem-solving, with a curious mindset and eagerness to learn.
• Effective communication skills to clearly report findings and collaborate within a team.

Key Program Facts:

• Program Length: 6 months
• Location: Lagoas Park, Oeiras (Lisbon)
• Working Model: In-office
• Full-Time preferred
• Expected start Date: May timeframe preferred

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You are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.

Key responsibilities include:

• Working closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.

• Working closely with customers, you will bring detailed requirements into the factory to enable R&D for strong, robust, and successful product development.

• Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.

• Driving the deployment and smooth execution of SLM solutions into customers’ projects.

• Enabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.

The impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and visionary ASIC Digital Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in design methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of protocols such as HBM, DDR, PCIe/CXL, AMBA and its applications. You can define and execute a new architecture for protocols such as UAL (Universal Accelerator Link). You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience. Your leadership skills enable you to guide and mentor teams, fostering innovation and excellence in all your projects.

What You’ll Be Doing:

• Defining and developing ASIC RTL design and verification at both chip and block levels.
• Creating and executing design plans for complex digital designs, particularly focusing on HBM, PCIe/CXL and AMBA protocols.
• Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
• Utilizing advanced design and verification methodologies and tools to achieve high-quality results.
• Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
• Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have:

• Enhancing the reliability and performance of Synopsys’ digital design processes.
• Driving innovations in HBM, PCIe/CXL and AMBA technology, contributing to the development of cutting-edge semiconductor solutions.
• Improving time-to-market for high-performance silicon chips through efficient methodologies.
• Building and nurturing a highly skilled development team, elevating overall project quality.
• Influencing strategic decisions that shape the future of Synopsys’ capabilities.
• Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You’ll Need:

• Extensive experience in ASIC RTL design.
• In-depth knowledge of HBM, PCIe, CXL, AMBA and similar IO protocols and their applications.
• Proficiency in advanced digital design tools and methodologies.
• Strong problem-solving skills and the ability to work independently.
• Excellent communication skills for effective collaboration with diverse teams.

Who You Are:

• A visionary leader with a strategic mindset.
• A mentor who fosters talent and encourages innovation.
• A proactive problem solver who thrives in complex environments.
• An effective communicator with the ability to convey technical concepts to a broad audience.
• A team player who values collaboration and diversity.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' design technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

You Are:

An experienced and visionary ASIC Digital Verification Architect, who is passionate about driving the future of semiconductor technology. You possess deep functional knowledge and expertise in verification methodologies, and you thrive in an environment where you can influence and implement strategic goals. Your background includes a comprehensive understanding of HBM or PCIe/CXL and its applications. You are a proactive problem solver, capable of working with minimal oversight, and you excel in communicating complex technical concepts to a diverse audience.

What You'll Be Doing:

• Defining and developing ASIC RTL design and verification at both chip and block levels.
• Creating and executing verification plans for complex digital designs, particularly focusing on HBM or PCIe/CXL.
• Collaborating with cross-functional teams to ensure seamless integration and functionality of designs.
• Utilizing advanced verification methodologies and tools to achieve high-quality verification results.
• Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement.
• Communicating with internal and external stakeholders to align on project goals and deliverables.

The Impact You Will Have:

• Enhancing the reliability and performance of Synopsys' digital verification processes.
• Driving innovations in HBM or PCIe/CXL technology, contributing to the development of cutting-edge semiconductor solutions.
• Improving time-to-market for high-performance silicon chips through efficient verification methodologies.
• Building and nurturing a highly skilled verification team, elevating overall project quality.
• Influencing strategic decisions that shape the future of Synopsys' verification capabilities.
• Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements.

What You'll Need:

• Extensive experience in ASIC RTL design and verification.
• In-depth knowledge of HBM or PCIe protocols and their applications.
• Proficiency in advanced verification tools and methodologies.
• Strong problem-solving skills and the ability to work independently.
• Excellent communication skills for effective collaboration with diverse teams.

Who You Are:

• A team member who encourages innovation.
• A proactive problem solver who thrives in complex environments.
• An effective communicator with the ability to convey technical concepts to a broad audience.
• A team player who values collaboration and diversity.

The Team You'll Be A Part Of:

You will join a dynamic and innovative team focused on advancing Synopsys' verification technologies. Our team is dedicated to excellence, collaboration, and continuous improvement. We work closely with various departments to ensure the successful integration and performance of our solutions. Together, we drive the future of semiconductor technology and make a significant impact on the industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits:

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Health & Wellness: Comprehensive medical and healthcare plans that work for you and your family.
• Time Away: In addition to company holidays, we have ETO and FTO Programs.
• Family Support: Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• ESPP: Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.
• Retirement Plans: Save for your future with our retirement plans that vary by region and country.
• Compensation: Competitive salaries.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Responsibilities:

Define and develop ASIC RTL design and verification at both chip level and block level. Collaborate with cross-functional teams to design, implement, and verify PCIe interfaces. Perform RTL coding, synthesis, and simulation to ensure design functionality and performance. Conduct design reviews and provide technical guidance to junior engineers. Work closely with physical design teams to ensure seamless integration and optimization. Debug and resolve design issues to ensure timely delivery of high-quality products.

Impact:

Contribute to the development of high-performance silicon chips that power next-generation technologies. Enhance the functionality and performance of Synopsys' PCIe solutions. Drive innovation and improve design methodologies within the team. Ensure the successful delivery of complex ASIC projects on time and within budget. Mentor and guide junior engineers, fostering a culture of continuous learning and development. Collaborate with cross-functional teams to deliver integrated and optimized solutions for our customers.

Requirements:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Extensive experience in ASIC digital design and verification. Strong knowledge of PCIe protocols and interfaces. Proficiency in RTL coding (Verilog/SystemVerilog) and simulation tools. Experience with synthesis, timing analysis, and formal verification.

Team:

Join a dynamic and collaborative team of engineers dedicated to designing and delivering high-performance silicon solutions. Our team focuses on innovation, quality, and continuous improvement, working together to solve complex technical challenges and deliver industry-leading products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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ASIC/SoC Presales Applications Engineer - 16648

Sunnyvale, California, United States

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Category: EngineeringHire Type: Employee

Job ID 16648Base Salary Range $184000-$276000Date posted 03/31/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned ASIC, SoC, or Chiplet Architect, Manager, or Design Engineer, bringing extensive expertise in IC Digital, Mixed Signal, or Analog Design. Your technical prowess is matched by your ability to engage and inspire customers, translating complex engineering concepts into clear, impactful solutions. You thrive in fast-paced, dynamic environments and are adept at navigating competitive landscapes. Your organizational skills and self-motivation ensure you deliver on ambitious goals, while your creative approach to problem-solving enables you to overcome challenges with finesse. You build trust and rapport quickly, fostering long-lasting relationships with both internal teams and external stakeholders. With a Bachelor’s (15+ years) or Master’s (11+ years) degree in a relevant field, you understand industry protocols such as SerDes, UCIe, PCIe, DDR, USB, MIPI, or Ethernet, bringing added value to each engagement. You are passionate about driving technology forward and contributing to customer success, ready to make a significant impact at Synopsys.

What You’ll Be Doing:

• Presenting Synopsys solutions to senior managers and technical stakeholders, showcasing the value and capabilities of our IP portfolio.

• Engaging with customers to understand their unique requirements and challenges, proposing tailored technical solutions that meet their needs.

• Positioning Synopsys competitively in technical discussions, articulating differentiators and advantages in the marketplace.

• Liaising between technical, marketing, and sales teams to ensure seamless communication and alignment on project objectives.

• Driving strategy and execution for technical solution design, influencing customer architectures and product adoption.

• Supporting sales and business unit negotiations with expert insight into technical feasibility, solution fit, and value proposition.

The Impact You Will Have:

• Lead customer engagements, ensuring Synopsys solutions align perfectly with client requirements and goals.

• Collaborate across global teams to deliver innovative, winning solutions that drive business growth.

• Accelerate adoption of Synopsys products and platforms within key customer accounts.

• Provide critical technical insight, shaping the design and success of customer chip projects.

• Drive customer and business success by enabling efficient, high-performance SoC and ASIC design.

• Ensure successful delivery of complex SoC projects across multiple regions, supporting Synopsys' reputation as a market leader.

What You’ll Need:

• Deep expertise in IC design, including Digital, Mixed Signal, or Analog domains.

• Experience in customer-facing roles, technical sales, or sales support within the semiconductor industry.

• Exceptional communication skills, able to convey complex technical concepts to diverse audiences.

• Strong organizational and project management abilities, driving multiple projects to completion.

• Solid understanding of major semiconductor IP product lines and industry protocols (SerDes, UCIe, PCIe, DDR, USB, MIPI, Ethernet).

Who You Are:

A creative problem solver and strategic thinker, you excel at collaborating with diverse teams and stakeholders. You are driven by a passion for technology, innovation, and customer success, bringing a positive, solutions-oriented mindset to every challenge. Your adaptability and leadership enable you to thrive in high-pressure situations, while your integrity and commitment build trust across all levels of the organization.

The Team You’ll Be A Part Of:

You’ll join a collaborative group dedicated to delivering groundbreaking chip design solutions using Synopsys IP. The team works closely with Sales, R&D, and Marketing, fostering a supportive and innovative environment where your ideas and expertise will help shape next-generation semiconductor products.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

As a Senior Software Engineer - Device Driver and Firmware, you will be responsible for designing, developing, and owning Linux device drivers (kernel/user-space interfaces) for platform hardware bring-up and runtime operation. You will also develop and maintain firmware components supporting board/module initialization, configuration, and operational readiness.

Key Responsibilities:

• Design, develop, and own Linux device drivers (kernel/user-space interfaces) for platform hardware bring-up and runtime operation
• Develop and maintain firmware components supporting board/module initialization, configuration, and operational readiness
• Build and maintain bring-up, validation, and regression workflows to ensure correctness, stability, and performance across releases
• Debug complex issues across hardware/software boundaries using Linux diagnostics (kernel logs) and systematic failure isolation approaches
• Collaborate with cross-functional teams to align driver/firmware behavior with platform requirements and integration constraints
• Drive automation using scripting/tooling to improve developer productivity, install/upgrade flows, and release robustness (packaging and deployment scripts)

Impact:

• Enable robust operation and integration of HAV platform hardware and software stacks
• Accelerate hardware bring-up and software validation for advanced semiconductor designs
• Increase platform reliability, stability, and performance through systematic debugging and validation
• Drive automation and efficiency in development, deployment, and release cycles
• Ensure seamless collaboration and integration across global engineering teams
• Contribute to industry-leading solutions that empower customers to innovate faster and smarter

Requirements:

• Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience
• 2–5 years of hands-on software development experience in device driver/firmware or Linux platform software
• Strong proficiency in C/C++/Embedded C/SystemC
• Experience with Linux-based driver development and debugging (kernel logs, device enumeration issues, driver initialization failures)
• Working knowledge of Python (or shell scripting) for automation, tooling, and workflow orchestration
• Familiarity with device tree concepts and hardware description for driver binding and initialization
• Exposure to firmware/bring-up flows, update/verification processes, and version alignment practices
• Experience with hardware interfaces such as PCIe and debugging enumeration/initialization issues
• Understanding of build systems, CI/regression infrastructure, and release packaging

Who You Are:

• Analytical thinker with a systematic approach to debugging and problem-solving
• Collaborative team player who communicates effectively across functions and cultures
• Detail-oriented and quality-focused, committed to robust, reliable solutions
• Adaptable and proactive, eager to learn and improve development practices
• Self-motivated, with a passion for technology and innovation

The Team You'll Be A Part Of:

You'll join a dynamic, global engineering team at Synopsys HAV, dedicated to advancing hardware/software co-verification platforms. The team focuses on delivering robust driver and firmware solutions, collaborating across functions to ensure seamless integration and exceptional customer outcomes. You'll work alongside experts in device drivers, firmware, validation, and automation, contributing to best-in-class technology that empowers the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will report key metrics and drive continuous improvement initiatives in Emulation IP quality and performance.

You will provide technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.

You will stay ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.

You will review and validate test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

You will collaborate cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.

You will mentor and guide junior engineers, fostering a culture of innovation and continuous improvement.

This role requires 10-20 years of relevant experience in emulation, verification, or IP product development.

You should have expert-level knowledge of PCIe and DDR interfaces, including protocol and verification strategies.

You should have extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

You should have demonstrated track record in leading IP product development initiatives with a focus on emulation.

You should have strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.

You should have outstanding communication skills, with the ability to influence and inspire change across diverse teams.

You should be adaptable and comfortable working in a fast-paced, matrixed, and international environment.

As a proactive and collaborative problem-solver with a passion for excellence, you will be a strong fit for this role.

You will join a dynamic, high-performing engineering team focused on IP development, emulation, and verification at the forefront of semiconductor innovation.

Our team is collaborative, cross-functional, and globally distributed, working together to solve complex challenges and deliver industry-leading solutions.

You will have the opportunity to collaborate with experts across multiple domains, drive impactful initiatives, and shape the future of digital design and verification at Synopsys.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

13752

Remote Eligible

No

Date Posted

12/16/2025

Responsibilities

• Reviewing Die, package, and PCB physical layout designs
• Modelling, simulating, and verifying high-speed interface performance against specifications
• Participating in the improvement of SI/PI methodology flows
• Collaborating and networking with other teams on task-oriented projects
• Independently driving SI/PI research and development activities

Impact

• Enabling SI/PI sign-off of high-speed interfaces for various Customer SoC/PKG/PCB designs targetting different applications
• Improve SI/PI methodology flows, increasing efficiency and accuracy
• Foster collaboration and innovation across globally distributed teams
• Drive research and development initiatives of next gen IP's (MRDIMM, LPDDR6, HBM4, UCIE) to stay ahead in the industry and offer guidance to our customers
• Support Synopsys' mission to lead in the Era of Pervasive Intelligence

Requirements

• Bachelor's or Master's degree in Electrical or Electronics Engineering
• Minimum of 8 years of relevant experience
• Proficient in Transmission line theory and time/frequency-domain analysis
• Experienced with SPICE and familiar with 3D field solvers
• Conversant with working of DDR, HBM, UCIE and PCIe/Ethernet interfaces
• Good verbal and written English communication skills
• Experience in scripting languages such as Python and TCL is a plus
• Familiarity with both Windows and Linux operating systems

Who You Are

You are a proactive and innovative engineer who thrives in a collaborative environment. You have a strong technical background and excellent problem-solving skills. Your ability to communicate effectively and work well with diverse teams makes you an asset to any project. You are dedicated to continuous learning and development, and your passion for technology drives you to stay ahead of industry trends. You are adaptable, detail-oriented, and committed to delivering high-quality results.

Team

You will be working with a group of highly-skilled, supportive, and globally spread-out teams. Our team is dedicated to driving innovation and excellence in SIPI analysis of high speed interface IP's. We value collaboration, continuous learning, and a can-do attitude. Together, we strive to develop the most advanced technologies and deliver exceptional results for our clients.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You will design end-to-end enterprise solutions, guide customers through technical decision-making, and partner with sales to expand Corsair's footprint in high-performance computing and AI-driven workloads. The ideal candidate merges advanced systems knowledge with customer-facing expertise to shape solutions, support sales, and accelerate adoption of Corsair's enterprise platforms.

**Key Responsibilities:*

• Platform & Product Strategy: Collaborate with product management, engineering teams, and HPC integration partners to shape the roadmap for workstations and HPC platforms. Identify and evaluate emerging technologies, market trends, and evolving workloads to inform product strategies and unlock new business opportunities.

• New Product Introduction (NPI): Develop and drive NPI readiness plans including technical documentation, sales enablement resources, and customer-facing solution guides. Ensure smooth product rollout by aligning engineering, marketing, support, and ecosystem partners.

• AI & Developer Ecosystem Engagement: Align with AI software partners, SDK/tool providers, and developer communities to build value-added integrations and optimize emerging AI workloads on Corsair platforms and provide architecture-level guidance to support AI, ML, and HPC applications.

• Customer Solutions & Technical Leadership: Design system- and application-level solutions based on customer requirements; perform diagnostics, optimization, and version upgrade management and act as a technical subject matter expert for enterprise accounts, providing advanced troubleshooting guidance and deployment support.

• Client Relationship & Escalation Management: Build and maintain strong customer relationships through effective communication, pre-sales support, and solution clarity. Manage hardware escalations by coordinating with internal teams and vendor partners to ensure timely issue resolution and serve as a trusted hardware and technical SME across internal and external engagements.

Qualifications:

• Bachelor’s degree in Computer Science, Engineering, or related field; equivalent practical experience (10+ years) considered.

• Extensive experience in high-performance computing, workstation architecture, or enterprise systems design.

• Strong background in Solutions Architecture, Sales Engineering, Product Marketing, or ODM platform development.

• Deep knowledge of Linux ecosystems, software build pipelines, and GPU computing technologies (NVIDIA CUDA, AMD ROCm, PCIe, InfiniBand).

• Excellent communication and leadership skills, with the ability to translate complex technical concepts into clear business value.

For roles that are based at our headquarters in Milpitas, CA: The starting base pay for this position is as shown below. The actual base pay is dependent upon a variety of job-related factors such as professional background, training, work experience, location, business needs and market demand. Therefore, in some circumstances, the actual salary could fall outside of this expected range. This pay range is subject to change and may be modified in the future.

Annual Salary Range $165,000—$180,000 USD

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Your work will involve hands-on troubleshooting and repair of compute, storage, interconnect and cooling systems to keep our large GPU/CPU cluster healthy and scalable. You will also be responsible for leading complex interventions, advanced diagnostics, guiding and uplifting L1s, process and automation, safety and compliance, and parts and logistics.

To be successful in this role, you will need 5+ years of experience in data center/server hardware or L2/L3 hardware support, with proven complex hands-on work in production (HPC/AI/Cloud at scale). You should have end-to-end hardware expertise, including comfort with CPU/memory/PCIe cards, NICs, PSUs, drives, network, power and cooling. You should also be confident in analyzing BMC/IPMI logs, linux software logs and crashes simple CLI checks, and have methodical root cause analysis skills.

The ideal candidate will be willing to travel between sites (Paris area or nearby regions, occasionally in Europe or US) and have a strong understanding of safety and discipline, including impeccable ESD/LOTO/PPE habits, zero rough handling, and clean, labeled, auditable work.

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Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.

As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.
• You will be responsible for micro-architecture using sophisticated verification methodologies.
• As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

Requirements:

• Bachelors or Master’s Degree (or equivalent experience)
• 3+ years of relevant verification experience
• Experience in architecting test bench environments for unit level verification
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Prior Design or Verification experience of Coherent high-speed interconnects
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful
• Strong background developing TB's from scratch using SV and UVM methodology is desired
• C++ programming language experience, scripting ability and an expertise in System Verilog
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong debugging and analytical skills
• Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

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Role Details:

• Designing, implementing, and delivering Embedded Controller (EC) firmware for client devices
• Integration of EC firmware with other platform firmware
• Providing technical support to the EC Chip vendors and OEMs/ODMs
• Partnering with the EC Chip vendors to ensure products work best with NVIDIA products
• Working with hardware teams to review HW architecture & schematics
• Collaborating with QA/Test architects to produce proper test tools and automation for qualifying firmware
• Developing collaterals for EC chip vendors and OEMs/ODMs

Requirements:

• Bachelor’s Degree or higher in Electrical Engineering or Computer Science (or equivalent experience), and 5+ yrs of proven experience, with demonstrated strong ability as individual contributor
• Experience implementing firmware in ARM Architecture
• Experience implementing system software in a Linux OS environment
• Experience implementing Embedded Controller (EC) firmware
• Solid experience in C/C++ development
• Solid understanding of low-level interfaces like GPIO/I2C/SPI/eSPI/PCIe/JTAG etc. PCIe enumeration, IO at platform level for notebooks
• Experience working closely with HW teams, ODMs and vendors to introduce and support notebooks
• Background in python for scripting, and debugging skills in embedded Linux operating environments
• Excellent written and oral communication skills, good work ethics, high sense of teamwork, love to produce quality work and a commitment to finish your tasks every single day

Nice to Have:

• Experience in Zephyr OS
• Expertise in Arm embedded architecture
• Experience in supporting Windows on Arm platforms

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Responsibilities:

• Architect power delivery systems for data center and super compute platforms, including multiphase VRMs and Intermediate Bus Converters (IBCs).
• Architect low voltage, high current (500A-1000A+) power rails for LPU, GPU and accelerator modules.
• Apply control theory principles to optimize power converter performance, stability, and transient response.
• Select and characterize power components including MOSFETs, inductors, transformers, and magnetic devices using vendor tools and configuration GUIs.
• Collaborate with ASIC and package teams to ensure power integrity across high-density PCB builds.
• Develop and complete lab validation plans using oscilloscopes and other test equipment.
• Build automation scripts to improve characterization efficiency and data analysis.
• Collaborate with power management ICs via I2C, SPI, and PCIe protocols for system integration and debug.
• Work with cross-functional teams including mechanical, thermal, firmware, and silicon build engineers.

Requirements:

• BS or MS in Electrical Engineering (or equivalent experience) with focus on power electronics.
• 5+ years of experience crafting power systems for data center, super compute, or high-performance computing applications.
• Deep expertise in multiphase VRM development and Intermediate Bus Converter (IBC) topologies, and control theory as applied to power converters.
• Hands-on experience with high-current (500A-1000A+) low voltage power delivery systems.
• Proficiency with Cadence tools for power integrity analysis and simulations, and experience with high-density PCB build and layout considerations.
• Familiarity with communication interfaces: I2C, SPI, PCIe.
• Proficient with scripting languages (Python, Perl) and Linux environment.
• Strong hands-on lab skills with oscilloscopes and power measurement equipment.
• Clear and effective communication skills, both written and verbal.

Preferred Qualifications:

• Experience with AI accelerator power delivery for platforms such as TPU, GPU, or similar architectures.
• Knowledge of advanced magnetic component build and optimization for high-density applications.
• Experience with power modeling and simulation tools.
• Background in EMI/EMC compliance and mitigation techniques.
• Proven track record in bringing power solutions from concept to mass production with experience collaborating with external vendors and suppliers.

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You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.

What You’ll Be Doing:

• Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.
• Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.
• Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.
• Collaborating with R&D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.
• Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.

The Impact You Will Have:

• Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.
• Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.
• Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.
• Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.
• Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.
• Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design

What You’ll Need:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.
• Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.
• 7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.
• Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).
• Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.
• Experience in Unix/Linux development environments.

Who You Are:

• Collaborative team player with excellent communication skills and a global mindset.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.
• Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.
• Adaptable and eager to stay updated with the latest industry trends and technologies.
• Customer-focused, with a dedication to supporting and enabling client success.

The Team You’ll Be A Part Of:

You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.

You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.

You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.

You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.

You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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ASIC Firmware Engineer, Modeling

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We are looking for an embedded engineer to help build firmware and associated modeling software for OpenAI’s in house AI accelerator. This role involves designing and developing drivers and functional models for a large array of HW components, writing high throughput and low latency firmware code, investigating bring-up and production issues.

Responsibilities

• Design and implement drivers for hardware peripherals, including those related to AI chips.

• Design and implement functional software models to simulate SoC uncore logic and enable FW testing against the model

• Design and implement low-latency and high throughput embedded SW to manage HW resources.

• Work with adjacent software and hardware teams to implement requirements, debug issues and shape future generations of the hardware.

• Collaborate with vendors to integrate their technologies within our systems.

• Bring up and debug firmware/driver on new platforms.

• Come up with processes and debug issues raised in the field.

• Set up monitoring, integration testing and diagnostics tools.

Qualifications

• 5+ years of experience working in embedded SW space.

• Ability to thrive in ambiguity and learn new technologies.

• Strong programming skills in C/C++ and/or Rust.

• Experience developing high throughput, low latency and multi-threaded code.

• Experience working with real time operating systems (RTOS).

• Experience developing hardware drivers and working with hardware

• Experience with HW/SW co-design

• Knowledge of common embedded protocols, e.g. UART, I2C, SPI, etc.

• Knowledge of microprocessor and common ARM architectures (e.g. AMBA) is a plus.

• Knowledge of PCIe, ethernet and other high BW communication protocols is a plus.

• Experience with GPUs or other compute hardware is a plus.

• Experience deploying large compute clusters is a plus.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

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Linux Kernels Software Lead

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $342K – $555K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

The Scaling team builds and optimizes large-scale infrastructure to enable next-generation AI workloads.

About the Role

We’re looking for a founding/lead Linux kernel developer to join our Scaling team. In this role, you’ll design and develop Linux kernel components, working at the intersection of hardware and software to unlock performance at scale.

Responsibilities

• Lead and bootstrap the development of our Linux kernel stack to support high-performance systems.

• Design and implement kernel drivers, including for functionality related to DMA, PCIe, NICs, and RDMA.

• Drive end-to-end development of system-scale networking, including required kernel and other low-level software.

• Collaborate with vendors to integrate their technologies within our systems.

• Bring up and debug the kernel on new platforms.

• Build userspace software to support integration, testing, diagnostics, and performance validation.

Qualifications

• Proven experience leading development within the Linux kernel.

• Deep knowledge of subsystems relevant to high-performance systems: PCIe, dma-buf, RDMA, P2P, SR-IOV, IOMMU, etc.

• Knowledge of subsystems and frameworks related to scale-out networking: ibverbs, ECN/DCQCN, etc.

• Strong programming skills in C, C++, Python, and Linux shell scripting; Rust experience is a strong plus.

• Experience working directly with engineering teams to define interfaces and tooling.

• Track record of managing vendor deliverables and technical relationships.

• Background in embedded systems development (bootloaders, drivers, hardware/software integration).

• Ability to thrive in ambiguity and build systems from scratch.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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What you'll do

• Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
• Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

What you need

• Bachelor's and/or masters with a minimum 10+yrs of Industry experience or equivalent
• At least 5+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)
• Solid understanding of ASIC design flows, including simulation/verification, RTL synthesis, floorplanning, physical design, and timing closure
• Hands-on expertise in integration and validation of High Speed SerDes IPs for PCIe, ETH, USB

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What you'll do

• Develop and implement high-performance PCIe-based designs on FPGA platforms, ensuring optimal functionality and efficiency.
• Collaborate closely with cross-functional teams to gather requirements, evaluate design tradeoffs, and deliver robust FPGA solutions that satisfy project goals.

What you need

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience in FPGA design and development.
• Proficiency in HDL languages such as Verilog.
• Strong expertise with industry-standard FPGA development tools like Vivado.
• In-depth understanding of digital design principles, including clock domains and timing analysis.
• Experience with high-speed interfaces (PCIe or Ethernet).
• Excellent analytical, debug, and problem-solving skills.
• Ability to collaborate effectively in a multi-disciplinary, team-based environment.
• Strong verbal and written communication skills.

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What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Partnering with design teams to define verification requirements
• Developing test plans from specifications
• Building and maintaining UVM testbenches and agents

What you need

• B.Sc./M.Sc. in a relevant engineering field
• 10+ years in ASIC/UVM verification

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.
• Designing and proposing advanced algorithms to calibrate and adapt transceivers for optimal performance.
• Correlating simulated performance with silicon measurements to ensure accuracy and reliability.
• Providing expert assistance to customers for system-level performance issues and troubleshooting.
• Collaborating with cross-functional teams of analog, digital, and hardware engineers throughout all stages of development.
• Contributing to lab testing and analysis for high-speed serial links, ensuring robust design validation.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

As a Sr Staff Engineer, you will be responsible for designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.

What you need

• MS/PhD in Computer Science, Electrical Engineering, or related field from a reputed institute, with 10+ years of relevant experience.
• Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.
• Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.
• Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.
• Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).
• Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).

Why this matters

• Accelerate the development of industry-leading prototyping systems, enabling faster time-to-market for cutting-edge ASIC designs.
• Enhance the functionality and reliability of Synopsys' HAPS and ProtoCompiler products through innovative hardware and software solutions.
• Drive customer satisfaction by delivering robust, scalable, and user-friendly prototyping tools that meet diverse engineering needs.
• Contribute to Synopsys' reputation as a leader in verification and prototyping technology, influencing industry standards and practices.

What you'll be doing

• Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.
• Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.
• Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.
• Developing and maintaining complex EDA software for high-performance prototyping systems.
• Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.
• Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.
• Supporting and enhancing existing products and features, responding to evolving customer needs with innovative solutions.
• Exploring and implementing new approaches to address current and future challenges, continuously learning and applying new technologies.
• Mentoring junior engineers, providing guidance and support to foster growth and technical excellence within the team.
• Collaborating independently and within cross-functional teams, networking with senior internal and external stakeholders.

Why you'll love this role

• Opportunity to work on cutting-edge projects and technologies.
• Collaborative and dynamic work environment.
• Professional growth and development opportunities.
• Recognition and rewards for outstanding performance.
• Comprehensive benefits and compensation package.

What you'll need to succeed

• Strong technical skills and knowledge in digital design, verification, and prototyping.
• Excellent problem-solving and debugging skills.
• Strong communication and collaboration skills.
• Ability to work independently and as part of a team.
• Adaptability and flexibility in a fast-paced environment.

How to apply

• If you're ready to make a meaningful impact and help shape the next generation of prototyping systems, Synopsys is the place for you.
• Apply now to join our team of talented engineers and contribute to the development of industry-leading prototyping solutions.

Benefits

• Comprehensive medical and healthcare plans that work for you and your family.
• Time away, including company holidays, ETO, and FTO programs.
• Family support, including maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
• ESPP, with a 15% discount on Synopsys common stock.
• Retirement plans, varying by region and country.
• Competitive salaries.

How we hire

• We're proud to be an equal opportunities employer and welcome applications from diverse candidates.
• Our hiring process typically involves a phone screen, followed by an interview with the hiring team.
• We're committed to providing a supportive and inclusive work environment, where everyone has the opportunity to grow and succeed.

Join our team

• If you're passionate about innovation and technology, and want to be part of a dynamic and collaborative team, apply now to join Synopsys.
• We can't wait to hear from you!

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What you'll do

You will design, develop, troubleshoot, and debug software programs for PCIe IP evaluation and test chip platforms.

• Designing, developing, troubleshooting, and debugging software programs for PCIe IP evaluation and test chip platforms.
• Developing scalable software tools, APIs, and architectures focused on evaluation software for Synopsys PCIe evaluation boards.

What you need

• Comprehensive expertise in PCIe protocol, SERDES, and hands-on experience with evaluation boards, silicon validation, or test chips.
• Advanced proficiency in Python, C++, or similar programming languages for embedded, driver, or system-level development.

Why this matters

Accelerate the evaluation and adoption of Synopsys's latest PCIe IP and test chips by delivering robust, user-friendly software tools. Enable seamless hardware bring-up and protocol validation, empowering both customers and internal teams to assess performance and compliance efficiently.

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What you'll do

Develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.

• Implement high-performance CPUs, GPUs, and interface IPs using industry-leading Synopsys tools such as RTLA, Fusion Compiler, DSO, and Fusion AI.

• Drive flow development and optimization to improve design quality and predictability.

• Collaborate with global experts to solve critical design challenges, ensuring the best possible QOR (Quality of Results).

• Contribute to the adoption and integration of advanced technologies and tool features in design implementation.

• Automate tasks and processes using scripting languages (TCL, Perl, Python) to streamline workflows and boost efficiency.

• Analyze and resolve issues related to synthesis, timing closure, power optimization, and constraints management.

What you need

• Minimum 7 years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why this matters

Shape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.

Enable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.

Enhance the predictability and simplicity of implementation processes for complex interface IPs.

Accelerate the adoption of next-generation design technologies and tools across the industry.

Drive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.

Empower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.

What you’ll need

• Minimum 7years of experience in physical design, with a focus on high-performance and low-power methodologies.

• Expertise in synthesis, timing closure, power optimization, constraints management, LEC, and STA flows.

• Hands-on experience with advanced process nodes (under 5nm) and complex IP implementation.

• Proficiency in scripting languages such as TCL, Perl, and Python for automation and process enhancement.

• Strong understanding of RTL, DFT, LDRC, TCM, VCLP, and PTPX; experience with interface IP controllers (UCie, PCIe, USB) is a plus.

Why you’ll love this role

• Collaborate with a talented team of engineers and experts to drive innovation and excellence in chip design and IP integration.

• Work on cutting-edge technologies and tools, shaping the future of the semiconductor industry.

• Enjoy a dynamic and supportive work environment that fosters growth, learning, and collaboration.

• Participate in professional development opportunities to enhance your skills and expertise.

• Contribute to the development of best-in-class methodologies and tools that drive industry-leading results.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

• Comprehensive medical and healthcare plans that work for you and your family.

• Time Away

• In addition to company holidays, we have ETO and FTO Programs.

• Family Support

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ESPP

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Retirement Plans

• Save for your future with our retirement plans that vary by region and country.

• Compensation

• Competitive salaries.

• Awards

• We're proud to receive several recognitions.

• Explore the Possibilities with Synopsys

• Search Synopsys Careers

• Join our Talent Community

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What you'll do

• Developing and writing high-quality user documentation for a variety of Digital and Mixed Signal IPs, including USB, PCIe, Ethernet, DDR, HDMI, and MIPI.
• Planning, organizing, and editing technical specifications, engineering schematics, application notes, and user guides to ensure clarity and usability.

What you need

• Bachelor’s or Master’s degree in Electronics, Science, Hardware, Computing, Software, Physics, Mathematics, Engineering, or a related technical discipline.
• 3-7 years of technical writing experience in the software or hardware industry, with proven ability to deliver high-quality documentation.

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What you'll do

Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.

Work with leading edge designs and teams to drive the industry best PPA for IP designs.

Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.

Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.

Work as a liaison between EDAG tool and IP design teams.

Continuously improve and refine design processes to enhance efficiency and performance.

What you need

BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.

Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.

Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.

Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.

Good analysis, debugging, and problem-solving skills.

Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.

Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

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What you'll do

Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.

• Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.

What you need

• MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.

Why this matters

Advance high-speed connectivity for enterprise and hyperscale applications worldwide.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR/ Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.

What you need

• 15+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.

XML job scraping automation by YubHub

What you'll do

Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.

Performing verification tasks for IP cores, including test planning and environment coding at both unit and system levels.

Developing and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.

Managing regression and ensuring adherence to verification methodologies.

Collaborating closely with RTL designers and a global team of verification engineers.

Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

What you need

BSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.

Experience in architecting verification environments for complex serial protocols.

Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.

Expertise in verification methodologies such as VMM, OVM, and UVM.

Knowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.

Familiarity with Verilog and scripting languages such as Perl, TCL, and Python.

Experience with IP design and verification processes, including VIP development.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.

What you need

• 15+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe/ DDR / Ethernet interfaces, including protocol and verification strategies.

XML job scraping automation by YubHub

What you'll do

• Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification for all functions, spanning both Controller and PHY domains.
• Reporting key metrics and driving continuous improvement initiatives in Emulation IP quality and performance.
• Providing technical leadership and expertise to define requirements for Emulation IP, ensuring its correct implementation and deployment within verification strategies.
• Staying ahead of evolving industry standards, interpreting future changes, ECNs, and specification errata, and integrating this knowledge into Emulation and Design IP teams.
• Reviewing and validating test plans for both Emulation IP and Design IP, guaranteeing best-in-class function, feature coverage, and product quality.
• Collaborating cross-functionally to optimize workflows, standardize methodologies, and ensure compliance with organizational goals.
• Mentoring and guiding junior engineers, fostering a culture of innovation and continuous improvement.

What you need

• 8+ years of relevant experience in emulation, verification, or IP product development.
• Expert-level knowledge of PCIe or DDR interfaces, including protocol and verification strategies.
• Extensive hands-on experience with Zebu or similar emulation platforms, particularly for IP verification.
• Demonstrated track record in leading IP product development initiatives with a focus on emulation.
• Strong background in cross-functional collaboration, with an ability to drive consensus and deliver results.
• Outstanding communication skills, with the ability to influence and inspire change across diverse teams.
• Adaptability and comfort working in a fast-paced, matrixed, and international environment.

XML job scraping automation by YubHub