{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/parasitic-optimization"},"x-facet":{"type":"skill","slug":"parasitic-optimization","display":"Parasitic Optimization","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a4f15f43-d71"},"title":"High-Speed SERDES Layout Specialist","description":"<p>We are seeking a highly skilled High-Speed SERDES Layout Specialist to join our team. As a key member of our design team, you will be responsible for designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.</li>\n<li>Developing floor plans, optimizing power distribution networks, and executing signal routing strategies with a focus on EMIR, parasitic minimization, and yield improvement.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>5+ years of hands-on experience in custom analog layout, with a focus on High-Speed SERDES (TX/RX/PLL) in deep submicron technologies.</li>\n<li>Proficiency in floor planning, power grid design, signal routing, and parasitic optimization.</li>\n<li>Expertise in industry-standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Mentor Calibre, Synopsys IC Compiler).</li>\n<li>Strong understanding of EMIR, DRC, LVS, ERC, ANT, ESD, DFM, and PERC verification methodologies.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a4f15f43-d71","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/high-speed-serdes-layout-specialist/44408/91299418752","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["custom analog layout","high-speed SERDES","floor planning","power grid design","signal routing","parasitic optimization","EDA tools","EMIR","DRC","LVS","ERC","ANT","ESD","DFM","PERC"],"x-skills-preferred":["package-level design","interposer and RDL layout"],"datePosted":"2026-03-06T07:22:03.742Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"custom analog layout, high-speed SERDES, floor planning, power grid design, signal routing, parasitic optimization, EDA tools, EMIR, DRC, LVS, ERC, ANT, ESD, DFM, PERC, package-level design, interposer and RDL layout"}]}