As a Principal AMS Layout Engineer, you will be working on high-speed SerDes IP layout and analog/mixed-signal circuits. You will be responsible for defining and managing layout scope, effort, schedules, deliverables, and customer-specific requirements. You will also be acting as the primary technical interface for customers and internal teams, presenting project status, risks, and mitigation plans.

Key responsibilities include:

• Defining and managing layout scope, effort, schedules, deliverables, and customer-specific requirements
• Accelerating layout development for high-speed SerDes IP to meet quality, schedule, and budget objectives
• Presenting project status, risks, and mitigation plans to customers and internal teams
• Gathering customer requirements and translating them into clear technical specifications and workflow improvements
• Performing hands-on debugging and root-cause analysis of complex layout issues
• Collaborating on layout approaches considering advanced packaging (2.5D/3D, interposers, bump strategy, etc.)

In this role, you will be part of the High-Speed Mixed-Signal IP Layout Team, which is known for its collaborative culture, modern tool ecosystem, and commitment to innovation.

The ideal candidate will have in-depth familiarity with high-speed SerDes layout and analog/mixed-signal circuits, as well as experience with multi-Gbps NRZ and PAM4 SerDes. You will also have expertise in high-speed/signal-integrity layout, ESD design constraints, custom digital layout, reliability-driven layout, and parasitic-aware layout.

As a Principal Engineer, you will be expected to innovate analog/mixed-signal layout methodologies using industry-standard tools and internal automation, and ensure signoff quality across DRC/LVS, EM/IR, reliability, parasitics, and tapeout readiness.

You will also be responsible for creating and maintaining technical documentation, workflow guides, specifications, and customer-facing deliverables, and ensuring documentation is scalable, maintainable, and supports long-term product evolution.

The High-Speed Mixed-Signal IP Layout Team is a dynamic and innovative group that works closely with experienced layout engineers, circuit designers, and CAD specialists to define best-in-class methodologies and deliver high-quality solutions to Synopsys customers worldwide.

If you are ready to make a meaningful impact at a global leader in semiconductor technology, Synopsys is your next destination.

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