These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a seasoned hardware engineering professional with a passion for advanced silicon package design and a proven track record in delivering innovative solutions for complex semiconductor challenges. With more than a decade of hands-on experience in package and interposer design, you possess a deep understanding of the latest advancements in 3DIC and multi-physics analysis.

Collaborating with cross-functional teams during early design stages to optimize and define SIPI (Signal Integrity/Power Integrity) performance requirements, including bump mapping and power estimation.

Designing and developing advanced silicon package solutions such as silicon interposers, RDL fanout packages, and silicon bridge packages.

Modeling and analyzing advanced package designs to ensure optimal electrical, thermal, and mechanical performance.

Representing Synopsys on business unit projects as a technical leader and subject matter expert in advanced packaging.

Resolving a wide range of design and integration issues using creative, data-driven approaches.

Supporting customer engagements in exploring and implementing advanced package solutions with Synopsys IPs.

Collaborating with global teams to share best practices and drive innovation in advanced packaging methodologies.

Empowering Synopsys and its customers to deliver next-generation, high-performance silicon solutions.

Accelerating the adoption of advanced packaging technologies that enable new levels of integration and energy efficiency.

Enhancing the performance, reliability, and manufacturability of Synopsys IP test chip packages.

Driving technical excellence and innovation in business unit projects that define Synopsys' leadership in the semiconductor industry.

Mentoring and guiding engineering peers, fostering a culture of knowledge sharing and continuous improvement.

Setting new industry standards for quality, performance, and innovation in advanced package design.

Building and strengthening customer relationships through expert support and collaboration.

XML job scraping automation by YubHub

Your primary responsibilities will include developing and integrating test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals. You will also partner with system architecture, chip design, and validation teams to define and deliver production-ready SLT and HVM test solutions.

In addition, you will drive custom SLT development to optimize system performance, power efficiency, and test coverage. You will oversee handler selection, enablement, and hardware integration, including PCB design, socket selection, and temperature control systems.

You will also improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM, and RMA processes. You will collaborate closely with Original Design Manufacturers (ODMs) on production enablement, sustaining, yield analysis, and DPPM reduction initiatives.

Finally, you will support silicon qualification and reliability testing (HTOL, Burn-in) at the system level.

To be successful in this role, you will need to have a strong understanding of electrical engineering principles, including signal integrity, data handling, and reporting. You will also need to have experience with lab equipment and measurement techniques for high-speed interfaces using high-speed scopes, probes, spectrum analyzers, BERTs, etc.

Additionally, you will need to have strong problem-solving skills, good communication skills, and the ability to work cooperatively in a team environment.

If you are a motivated and experienced Senior Post Silicon Validation Engineer looking for a new challenge, please apply today!

XML job scraping automation by YubHub

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

Benefits

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role, you will:

• Lead system signal integrity (SI) design for AI supercomputer product in the data center application.

• Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies

• Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity

• Perform simulation and modeling to identify and troubleshoot signal integrity issues

• Lead system interconnect design, bring up and qualification

• As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.

You might thrive in this role if you:

• Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications

• Have a strong bias toward action, and won’t take no for an answer.

• Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level

• Have experience with PCB, connector and cable design

• Have a strong intrinsic desire to learn and fill in missing skills; and an equally strong talent for sharing that information clearly and concisely with others.

• Are comfortable with ambiguity and rapidly changing conditions.

XML job scraping automation by YubHub

What you'll do

• Early design stage collaboration to optimize and define requirements for SI&PI performance (e.g., bump maps)
• Support 5~7 PHY Test Chip Package designs per year
• Help customers explore their package solution space options with Synopsys IPs
• Model extract and analyze package substrate designs
• Coordination of package design phases and flow
• Resolves a wide range of issues in creative way
• Provides regular updates to manager on project status
• Represents the organization on business unit projects

What you need

• Minimum of 10+ years of relevant experience
• Good verbal and written English communication skills required
• Advanced circuit and transmission line theory knowledge required
• 3D Electromagnetic modeling experience (e.g. HFSS, or similar tool)
• Familiarity with both Windows and Linux operating systems
• Bachelor’s degree in electrical, electronic engineering or equivalent

XML job scraping automation by YubHub