Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.

You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

As a member of our high-performing Customer Application Services team, you will collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.

Responsibilities:

• Support customers in enjoying Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge.
• Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).
• Collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.
• Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.
• Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.

Key Qualifications:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),
• Tool knowledge (preferred): STA (Primetime, Tempus)

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You will work alongside system architects, chip and board designers, software/firmware engineers, HW/SW applications engineers, process/reliability specialists, ATE engineers, and operations in a dynamic and high-energy work environment to bring industry-defining products to market.

Your responsibilities will include:

• Collaborating with cross-functional teams to craft essential next-generation product features that are important for performance, power optimization, and power management.
• Collaborating to craft tools for post-silicon work, build post-silicon methodologies to characterize silicon power, correlate silicon behavior with simulation.
• Working with various Arch & Design teams to come up with test plans of new features.
• Collaborating with other validation & bring-up teams to bring up/characterize silicon power and power saving features.
• Working with design & estimation teams to correlate with pre-silicon expectation, work with HW and SW teams to do the vital tuning and optimization of silicon power.
• Developing power consumption models to be used in binning, productization, and customer application notes, characterize and develop various power control mechanisms together with Arch/Design/SW teams.

We need to see:

• B. Tech or M. Tech in Electronics Engineering stream, with 3+ years related work experience, excellent problem-solving, collaborative, and interpersonal skills.
• Strong understanding of aspects related to silicon power and performance, technology node impacts, Hardware and Software interactions at system level.
• Hands-on experience with silicon bring up, validation, and productization, good knowledge in board and system design considerations, Power supply design.
• Very good problem-solving and hardware debugging skills, very good data analysis and logical reasoning skills.
• Strong familiarity with HW lab environment and understanding of various lab equipment.
• Experience in working with windows. Linux exposure is highly preferred.
• Working experience with scripting languages like perl and/or python is a plus point.
• Must be a great teammate and ready to collaborate with global teams from diverse cultural backgrounds in a high-energy environment.
• Exposure to critical path analysis, power analysis, process technologies, transistor/device physics, silicon reliability, and aging mechanisms.
• Background with power supply and substrate noise analysis and mitigation. Exposure to digital design, circuit analysis, computer architecture, BIOS, drivers, and software applications.

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Role Details:

Responsibilities:

• Develop physical design methodologies for rail analysis and signoff.
• Come up with unique and creative solutions for pioneering IR analysis and signoff that are needed for NVIDIA chips.
• Craft workflows and tool methodologies for power and noise analysis across multiple projects.

Requirements:

• Master's degree or equivalent experience in Electrical Engineering or related field.
• Minimum 5+ years of experience in EMIR flow methodology development and support.
• Strong understanding of all aspects of EMIR analysis and signoff.
• Familiar with hierarchical design approach and hierarchical signoff.
• Experience with shift-left methodologies for EMIR optimization and convergence earlier in the chip build cycle.
• Ability to collaborate across teams: Strong interpersonal, communication and teamwork skills, with a track record of working closely with hardware and design teams to facilitate EMIR signoff
• Proficiency in programming and scripting languages, such as TCL, Perl, Python, and C++.

Ways to Stand Out:

• Experience in crafting custom workflows from scratch.
• Adaptability and problem-solving skills: Ability to thrive in a dynamic, fast-paced environment where quick thinking and creative solutions are often required.
• Experience using AI tools to improve capabilities in the power integrity domain, such as automating analysis and improving tool/flow features

You will also be eligible for equity and benefits.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15231

Remote Eligible

No

Date Posted

02/15/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• An experienced and passionate Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.

• You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.

• Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.

• You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.

• You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.

• You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.

What You’ll Be Doing:

• Leading NRZ/PAM4 Serdes analog design transceiver solutions.

• Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.

• Collaborating with silicon test and debug experts for Sim2Sil correlation.

• Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.

The Impact You Will Have:

• Driving innovation in mixed-signal advanced analog serdes design.

• Enhancing the performance and efficiency of high-speed physical interfaces.

• Contributing to the development of cutting-edge technology in High Speed PHY IP.

• Improving quality and robustness of design through collaboration and Sim2Sil correlation.

What You’ll Need:

• BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.

• Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.

• Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .

• Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters

Who You Are:

• Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.

• Experience with PLL designs and high-speed digital circuit design.

• Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.

• Familiarity with digitally assisted analog circuit techniques.

• Capable to drive technical decision and tradeoff with customer focus

The Team You’ll Be A Part Of:

Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.

You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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What you'll do

• Providing world-class support to customers and channel partners, ensuring effective usage and satisfaction with Apache BU simulation products focused on Power, Power Integrity, and Reliability.
• Applying advanced knowledge in custom circuit analysis, RTL design, high-performance VLSI design, standard cell physical layout, power-grid extraction, timing analysis, noise analysis, and voltage drop effects to solve complex SoC challenges.

What you need

• Bachelor’s degree in Electrical Engineering (BSEE) with at least 6 years of experience, Master’s degree (MSEE) with 4 years, or PhD with 2 years in VLSI design.
• Expertise in custom circuit analysis, standard cell physical layout, timing and noise analysis, and voltage drop effects using CAD tools.
• Strong technical knowledge of EDA tools for layout, STA, Extraction (SPEF/DSPF), and Spice simulation.

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What you'll do

• Provide expert support and training to customers on Totem and related Semiconductor Business Unit simulation products, ensuring high productivity and satisfaction.
• Independently coordinate and manage support for multiple customer designs through tape-out, verifying design quality and compliance with expectations.
• Apply advanced knowledge in analog circuit analysis, VLSI design, power-grid extraction, noise analysis, and ESD to solve complex SoC challenges.

What you need

• Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) with at least 3 years of relevant experience.
• Advanced expertise in custom circuit analysis & design, physical layout, noise analysis, voltage drop effects, and ESD using CAD tools.
• Strong technical knowledge of EDA tools, especially for layout and analog circuit extraction (SPEF/DSPF).
• Proficiency in UNIX operating systems and scripting languages such as Perl, Tcl, or Python for troubleshooting and utility development.
• Excellent verbal and written communication skills in both English and Mandarin, with the ability to convey complex concepts clearly.

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