Reporting to the Executive Director, Market Access Operations and serving as a core member of the leadership team, this role oversees the end-to-end lifecycle of market access contracts,spanning drafting, negotiation, and regulatory compliance to enable both patient access and value creation.

The leader will drive contract implementation, rebate and chargeback processing, and revenue-leakage analysis, directing high-performing teams to improve efficiency in close partnership with payers, wholesalers, and Pharmacy Benefit Managers (PBMs).

Importantly, this role will be accountable for steering the organization through a period of change as we adapt rebate constructs in light of evolving policy updates, setting direction, aligning stakeholders, and ensuring disciplined execution to safeguard market access contracts and sustain operational excellence.

**Key Responsibilities:"

• Operational Management: Oversee the full contract lifecycle,from drafting through execution and renewal,ensuring timely, efficient implementation of pricing strategies and policies aligned with business objectives.

• Contract Administration: Lead administration of Market Access customer contracts, securing favorable terms and ensuring compliance with Gross-to-Net (GTN) implications and Fair Market Value (FMV) assessments.

• Operational Excellence: Drive economic transparency, accurate processing, and SOX-compliant auditability for payments,including rebates, service fees, data purchases, and outcomes-based arrangements,within a robust, end-to-end framework emphasizing internal controls, data integrity, and disciplined documentation.

• Launch Readiness & Supply Chain: Coordinate cross-functional product launch activities, manage wholesaler orders, and ensure supply continuity.

• Change Leadership & Team Management: Lead a large, high-performing team through a period of change, ensuring processes reflect best practice and evolve in step with a rapidly changing external landscape. Make staffing decisions and effectively assess and coach managers to optimize team composition, capability, and performance.

• Process Improvement: Institutionalize standardized operating processes while continuously identifying and implementing enhancements to improve efficiency, accuracy, and compliance.

• Compliance & Risk Management: Ensure adherence to all laws, regulations, and policies governing AZ Contract and Trade Operations, proactively manage risks, and participate as a voting member of the GTN Governance Committee.

• Performance Metrics & Analytics: Develop and operationalize KPIs and dashboards to monitor contract performance, financial liabilities, and account/partner performance; deliver data-driven insights on market trends to support strategic planning and decision-making.

• Cross-Functional Collaboration: Partner with Legal, Finance, Brand, and Market Access teams to align contracting strategies with commercial goals.

• Stakeholder Engagement: Build and maintain strategic relationships with key external stakeholders,including payers, wholesalers, and industry associations,and manage vendor and third-party partnerships.

Requirements:

• Bachelor’s degree in relevant field (Business, Finance, or Life Sciences).

• 8 years in market access, access strategy or finance with at least 5 years in a leadership role. Proven track record in leading and developing high-performing teams

• Strong understanding of payers, specialty pharmacy models (including limited distribution networks), 3PL operations, and group purchasing organizations.

• Proficiency in contract management systems (e.g., Model N, Salesforce), ERP systems (e.g., SAP, Oracle), and data analytics tools (e.g., Excel, PowerBI).

• Successfully leads cross-functional projects, manages vendor relationships, and negotiates in matrixed organizations.

Preferred Requirements:

• An Advanced Degree (MA/MS/MBA) or equivalent experience is preferred

• Pharmaceutical trade, distribution, or contracting roles

• Detailed understanding of AZ business model with knowledge of brand team operation, brand planning, and sales model.

Why AstraZeneca?

At AstraZeneca when we see an opportunity for change, we seize it and make it happen, because any opportunity no matter how small, can be the start of something big. Delivering life-changing medicines is about being entrepreneurial - finding those moments and recognizing their potential. Join us on our journey of building a new kind of organization to reset expectations of what a bio-pharmaceutical company can be. This means we’re opening new ways to work, pioneering cutting edge methods and bringing unexpected teams together.

Interested? Come and join our journey. When we put unexpected teams in the same room, we unleash bold thinking with the power to inspire life-changing medicines. In-person working gives us the platform we need to connect, work at pace and challenge perceptions. That's why we work, on average, a minimum of three days per week from the office. But that doesn't mean we're not flexible. We balance the expectation of being in the office while respecting individual flexibility.

Join us in our unique and ambitious world. Ready to make a difference? Apply now and join us on this exciting journey

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The ideal candidate should have a proven track record in developing and maintaining Java-based front-end applications in the finance sector. Exceptional team collaboration skills and the ability to work effectively with colleagues across global time zones are crucial.

Millennium strongly prioritizes our synergistic culture, which revolves around teamwork and low egos. You should possess the ability to work in a fast-paced environment both collaboratively and individually while managing multiple projects simultaneously.

The successful individual will have a strong sense of urgency, emotional intelligence, and prioritize a high-caliber end-user experience.

Qualifications:

• Bachelor’s degree in computer science or comparable
• 7+ years of professional experience with Core Java and Java Swing, electronic trading systems and/or trader workstations environment strongly preferred.
• 5+ years of experience working with HTML, JavaScript, CSS, and JQuery
• Deep understanding of multithreading and distributed systems within a high performance, latency-sensitive environment
• Strong knowledge of unit testing frameworks and continuous test-driven development practices
• Enterprise level experience with design patterns such as MVC, MV, MVP
• Enterprise level experience with RESTful web services
• Previous experience liaising with non-technology stakeholders, polished and proactive communication skills

Beneficial/Ideal Technology Experience:

• EXT-JS, AngularJS, AJAX, JSON experience is very beneficial
• Knowledge of equities, futures, options and other asset classes is preferred
• Enterprise level experience with OMS architecture and design is preferred
• Experience with messaging middleware, Solace preferred
• Experience with relational and NoSQL databases. MongoDB preferred
• Experience working with financial data, including reference data, market data, order/execution and positions data.
• Experience working with Cloud: AWS (preferred), GCP or Azure

Millennium pays a total compensation package which includes a base salary, discretionary performance bonus, and a comprehensive benefits package. The estimated base salary range for this position is $175,000 to $250,000, which is specific to New York and may change in the future.

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Our team is fast-paced and agile, comprising engineers, a product manager, and designer. We work closely together to deliver innovative solutions that meet the needs of our customers.

Responsibilities:

• Design and develop high-quality iOS applications using Swift and Objective-C
• Collaborate with the product manager and designer to define and prioritize features
• Work with the engineering team to ensure seamless integration with other components
• Participate in code reviews and contribute to the improvement of our codebase
• Mentor junior engineers and help them grow in their careers

Requirements:

• 8+ years of professional iOS development experience
• Excellent communication and collaboration skills
• Experience building public or internal mobile APIs/SDKs and working with Swift and Objective-C
• Experience with UIKit, SwiftUI, programmatic Auto Layout, and iOS design patterns (MVVM, reactive programming)
• Experience with Unit/UI/integration/performance testing on iOS (Quick, Nimble, XCTest, XCUITest, etc.)
• Experience with Realm database or similar mobile NoSQL solutions
• End-to-end ownership of mobile applications or SDKs
• Experience with mobile CI/CD pipelines (GitHub Actions)

Preferred Qualifications:

• 1+ years of experience in identity and access management (IAM) domain, particularly with Auth0 Guardian SDK or similar MFA/authentication solutions
• Experience with iOS security best practices, including cryptography (RSA, CommonCrypto), biometric authentication (Face ID/Touch ID), iOS Keychain, Authentication Service framework, and secure data storage
• Experience with reactive programming frameworks (ReactiveSwift, Combine) and migrating legacy architectures to MVVM patterns
• Experience with infrastructure-as-code tools (e.g., Fastlane, Swift Package Manager, Snyk, or Terraform)

If you are a motivated and experienced iOS engineer looking to join a dynamic team, we encourage you to apply.

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Okta secures AI by building the trusted, neutral infrastructure that enables organisations to safely embrace this new era.

We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work.

In this role, you will be tasked with providing hands-on implementation and deployment services to our customers. We are looking for an experienced, enthusiastic and hands-on leader who can rapidly learn the Okta platform, our technology and the value proposition that we bring to customers of all sizes.

Duties and responsibilities:

• Work hands on with Okta customers, primarily in a post-sales role, to provide innovative consulting services.
• Gather, analyse, and document post-sales requirements.
• Communicate to customers and partners at the technical and/or functional level appropriate for the situation.
• Be dedicated to providing excellent design and deployment solutions resulting in extraordinary customer satisfaction.
• Be prompt and deliver high quality service and leadership to align with customer goals and requests.
• Manage project scope, schedule, status, and documentation.
• Mentor and train customers on the service.
• Act as a liaison between Customers and Product Management to drive product development.
• Lead interaction and collaboration with other Okta teams such as Engineering and Support as needed to address escalated issues.
• Interact with management and other roles within the customer organisation and Okta.
• Collaborate with the sales team on existing customers up-sell and cross-sell opportunities.
• Perform hands on technical design, configuration, and troubleshooting of the Okta service.
• Shape and Influence Okta’s growth and scalability, by designing new offerings, and finding new ways to deliver amazing customer satisfaction.
• Manage multiple concurrent deployment projects.
• Apply knowledge of technologies and protocols to support identity federation and robust access control models, such as SAML 2.0, WS-Federation, OAuth, and OpenID Connect.
• While providing customer service, apply knowledge of cloud architectures as well as complex enterprise on-premise IT landscapes.
• Apply software development experience (Java, Ruby, .Net, PHP, REST/JSON, etc) when working with customers.
• Utilise knowledge of typical enterprise identity life cycle management processes and standards.
• Apply experience with JavaScript and one of the major JavaScript MVC frameworks (Backbone, Angular, Ember, React, etc.) when working on customer integrations.
• May provide mentoring, guidance, and expertise to less experienced team members.
• Ensure quality and time management processes are followed by team (e.g., change controls, time tracking).
• Commit to and use a knowledge repository for deployment standard methodologies and other customer ideas as continuous improvement.

Minimum REQUIRED Knowledge, Skills, and Abilities:

• 5-7 years experience as a technical consultant delivering solutions to external customers.
• Experience with technologies and protocols to support identity federation and robust access control models (e.g., OAuth, OpenID Connect, SAML 2.0, WS-Federation).
• Software development experience (Java, Ruby, .Net, PHP, REST/JSON, etc).
• Some knowledge of enterprise web technologies, security and cutting-edge infrastructures.
• Experience with JavaScript and one of the major JavaScript MVC frameworks (Backbone, Angular, Ember, React, etc.)
• Ability to work independently and multi-functionally supporting the development of client work you're doing.
• Knowledge of typical enterprise identity life cycle management processes and standards.
• Ability to Multi-task and manage multiple customer engagements is a requirement.
• Able and willing to be a hands-on contributor.
• Superb communication skills, including issue tracking, triaging and crisis management.
• Experience in Process Improvement, Decision-making, Managing Processes, Planning, Analyzing Information and Developing Standards.

Additional requirements:

• This position requires the ability to access federal environments and/or have access to protected federal data. As a condition of employment for this position, the successful candidate must be able to submit documentation establishing U.S. Person status (e.g. a U.S. Citizen, National, Lawful Permanent Resident, Refugee, or Asylee. 22 CFR 120.15) upon hire.
• Must be available to work onsite at Fort Meade.
• Must have active Secret Clearance.

Nice to have:

• Experience in designing and implementing security and identity management solutions to support critical systems and business programs.
• Experience in delivering Okta implementations for organisations.
• Mobile development experience preferred (iOS and Android).

Problem Solving:

• Exhibits confidence and an extensive knowledge of emerging industry practices when solving business problems.
• Asks probing questions to elicit facts and clarify a situation.
• Identifies critical issues with ease.
• Engages appropriate resources to obtain information, seek suggestions and acquire assistance.
• Pushes creative thinking beyond the boundaries of existing industry practices and customer mindsets.

Communication:

• Communicates with internal and external customers and all levels of management.
• Effectively communicate technical information to non-technical audiences.
• Delivers informative, well-organised presentations.
• Understands how to communicate difficult/sensitive information thoughtfully.
• Uses active listening skills to figure out and understand the customer's business goals, objectives and priorities.

Team and Customer Interaction:

• Facilitates effective team interaction.
• Communicates effectively with customers to identify needs and evaluate alternative technical solutions with customers.
• Continually seeks opportunities to increase customer satisfaction and deepen client relationships.
• Manages client expectations effectively.

Education:

A Bachelor's degree (or equivalent) in Computer Science, Information Technology or related discipline required.

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You are a good fit for this role if you have 5+ years of software development experience. You have excellent communication and collaboration skills. You have experience building public or internal mobile APIs/SDKs and working with Java and Kotlin. You have experience with XML layouts, View Binding, and Android Views (ViewModels, LiveData). You have experience with unit/UI/integration/performance testing on iOS (JUnit, Robolectric, Mockito, MockK, etc.). You have experience with Realm database or similar mobile NoSQL solutions. You have experience with mobile CI/CD pipelines (Github Actions).

Bonus points if you have 1+ years of experience in identity and access management (IAM) domain, particularly with Auth0 Guardian SDK or similar MFA/authentication solutions. You have experience with Android security best practices including cryptography (RSA, PBKDF2), biometric authentication, Android KeyStore, and ProGuard/R8 optimization. You have experience with Dagger 2 dependency injection and migrating legacy MVP architecture to MVVM patterns. You have experience with infrastructure-as-code tools (e.g., Fastlane, Gradle, Snyk, or Terraform).

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As a Product Manager, you will work with researchers to understand what's emerging and what it means for users. You will identify nascent research capabilities that could become transformative consumer products and lead 0-to-1 product development from research to internal prototypes to shipped products.

Responsibilities:

• Work with researchers to understand what's emerging and what it means for users
• Identify nascent research capabilities that could become transformative consumer products
• Lead 0-to-1 product development from research to internal prototypes to shipped products
• Define product strategy for consumer initiatives that push beyond our current offerings
• Creatively build MVPs and prototypes to validate product-market fit with the lowest cost possible
• Lead vision, strategy, roadmap, and execution of frontier technologies that leverage the latest AI capabilities to solve real-world problems

Requirements:

• Have a track record as a founder or 8+ years in product management, with experience launching new products and scaling existing products
• Can’t stop thinking about new ways to build products on top of the latest model capabilities
• Possess a deep technical background with experience working cross-functionally with engineering teams to ship technical products
• Have the ability to navigate and execute amidst ambiguity, and to flex into different domains based on the business problem at hand, finding simple, easy-to-understand solutions
• Experience launching ambitious consumer products that have found distribution or commercial success
• Think creatively about the risks and benefits of new technologies, and think beyond past checklists and playbooks
• Stay up-to-date and hands-on with emerging research and industry trends
• Prototype with AI tools like Claude Code

Annual compensation range for this role is $385,000-$460,000 USD.

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Key Responsibilities: Perform surface finishing operations on composite parts, including wet layup, filling, sanding, spraying gelcoat and refining the surface. Mix and apply surface fillers, and gelcoat per process requirements Sand and smooth complex contours while maintaining tolerance and surface quality Identify and repair surface defects such as pinholes, delamination, or surface voids using tap tests Prepare parts for painting, bonding, or assembly through proper surface treatment Follow detailed work instructions, drawings, and engineering specifications Maintain cleanliness and organization in finishing areas; manage dust control systems Collaborate with the quality team to ensure finished parts meet visual and dimensional standards Follow procedures and track time on a tablet.

Requirements: 2+ years of experience in marine composite finishing, surfacing, or similar hands-on fabrication work Strong experience with sanding tools, fairing materials, and manual finishing techniques Ability to achieve Class A or near-Class A surface finishes (preferred but not required) High attention to detail and patience for repetitive, fine-surface work Familiarity with epoxy-based fillers, primers, and surface prep chemicals Ability to read and interpret technical drawings and work instructions U.S. Person (citizen or permanent resident) required due to DoD-related work

Preferred Qualifications: Experience in marine composite surfacing Familiarity with MIL-SPEC or AS9100 quality standards Experience using DA sanders, longboards, and vacuum-assisted finishing tools Understand how to use Binks & MVP spray equipment Background in paint prep or bonded surface prep is a plus Experience working with gel coats, topcoats, or marine-grade finishes

Benefits: Medical Insurance: Comprehensive health insurance plans covering a range of services Saronic pays 100% of the premium for employees and 80% for dependents Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care Saronic pays 99% of the premium for employees and 80% for dependents Time Off: Generous PTO and Holidays Parental Leave: Paid maternity and paternity leave to support new parents Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses Retirement Plan: 401(k) plan Stock Options: Equity options to give employees a stake in the company’s success Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

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You will focus on large molds: loading dry material & stringers, installing vacuum manifolds, bagging, drop tests, leak detection, maintaining vacuum catch pots, mixing resin and MEKP to appropriate ratios, and other infusion techniques.

This hands-on role is critical to our manufacturing process and directly impacts product reliability and performance.

Key Responsibilities:

• Attention to detail and commitment to industry-leading standards
• Prepare molds and tooling for composite layup and infusion
• Perform precise hand layups using dry fiber materials
• Set up and execute vacuum-assisted resin infusion processes
• Mix and handle resins, hardeners, and other composite materials in accordance with safety protocols
• Ensure each fiberglass layer is installed to prevent bridging, wrinkling, and resin richness
• Install core with minimal gaps
• Maintain a clean, organized, and safety-compliant workspace
• Interpret technical drawings, layup schedules, and process documentation using a tablet
• Collaborate closely with engineering and quality teams to iterate on part design and manufacturability
• Document work performed and identify process improvements or quality issues
• Work with a sense of urgency
• Mix putty, debur surfaces to prep for dry loading fiberglass and duties as assigned

Requirements:

• 2+ years of hands-on experience with composites manufacturing, particularly resin infusion at a high rate boat building factory
• Strong attention to detail, manual dexterity, and a quality-first mindset
• Experience with vacuum bagging hull and decks
• Ability to work with minimal supervision in a fast-paced, iterative environment
• Familiarity with vinyl ester and polyester resins, carbon fiber, dry fiberglass
• Comfortable using trimming tools, grinders, and measurement instruments
• Able to read technical drawings and follow standard operating procedures
• U.S. Person (citizen or permanent resident) required due to DoD contract work

Preferred Qualifications:

• Ability to use a MVP Hight Output System
• Experience with marine composite fabrication
• Familiarity with AS9100 or ISO 9001 quality systems
• Forklift or crane certification a plus

Additional Information

Benefits: Medical Insurance: Comprehensive health insurance plans covering a range of services Saronic pays 100% of the premium for employees and 80% for dependents Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care Saronic pays 100% of the premium under the basic plan for employees and 80% for dependents Time Off: Generous PTO and Holidays Parental Leave: Paid maternity and paternity leave to support new parents Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses Retirement Plan: 401(k) plan with company match Stock Options: Equity options to give employees a stake in the company’s success Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage Pet Insurance: Discounted pet insurance options including 24/7 Telehealth helpline Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

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Responsibilities:

• Develop new product features that leverage the network model to help users visualise their network, understand how it behaves, see how it has evolved, answer specific questions, and plan changes
• Design the data model for new product features
• Propose and implement REST APIs to support the Forward Networks web application and to publish to customers
• Constructively review product designs, technical design documents, and code changes

Requirements:

• At least 5+ years of full lifecycle software development experience
• Expertise in Java (version 17 or above)
• Considerable experience with a dependency injection framework such as Guice or Spring and a talent for writing (and refactoring) code for testability
• Deep understanding of REST API design fundamentals and best practices
• Proficiency in SQL and relational database schema design
• Strong object-oriented design and development skills
• Familiarity with the principles of functional programming
• Good communication skills

Nice to have:

• Experience with the Spring Web MVC framework or Spring Boot
• Some experience with other JVM languages such as Groovy, Kotlin, or Scala
• Some experience with TypeScript or modern JavaScript

This position is a regular, full-time opportunity with Forward Networks in Bangalore, India.

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Key Responsibilities

• Design, develop, and optimize FPGA-based digital systems for real-time defense applications
• Implement RTL designs (VHDL, Verilog, SystemVerilog) for high-speed data processing
• Perform simulation, synthesis, timing analysis, and timing closure
• Develop and integrate DSP algorithms in hardware (e.g., FFTs, filters, modulation)
• Interface with high-speed ADCs/DACs, RF front ends, and embedded processors
• Support hardware bring-up, debugging, and validation in lab environments
• Collaborate with RF, systems, and software engineers to ensure system performance
• Document designs, requirements, and verification results

Required Qualifications

• Bachelor’s degree in Electrical or Computer Engineering (or related field)
• Minimum of 2 years' professional experience within the aerospace & defense industry
• Minimum 2 years' experience using FPGA toolchains (Xilinx Vivado, Intel Quartus)
• Proficiency in HDLs (VHDL, Verilog, or SystemVerilog)
• Strong understanding of digital design fundamentals (timing, clock domains, pipelining)
• Experience with simulation/verification tools (ModelSim, Questa, etc.)
• Ability to obtain and maintain a U.S. security clearance

ITAR Regulations

• To conform to U.S. Government technology export regulations, including the International Traffic in Arms Regulations (ITAR), applicant must be a US Citizen, Green Card holder, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

Bonus Points

• Experience with defense systems (radar, EW, communications)
• Knowledge of digital signal processing (DSP) implementation and fixed-point math
• Proficient in scripting languages (Tcl, bash, Python)
• Familiarity with embedded software integration on SoCs
• Experience with high-speed interfaces (JESD204, PCIe, Ethernet, DDR)
• Familiarity with SoC platforms (e.g., Xilinx Zynq, RFSoC)
• Understanding of RF signal chains and systems

Additional Information

CX2 is a next-generation defense technology company securing spectrum dominance for the United States and its allies. We build AI-enabled hardware and software platforms to detect, disrupt, and defend the electromagnetic spectrum across land, air, sea, and space. Our systems are deployed in the most contested operational environments in the world. We’re backed by leading venture investors in the defense ecosystem and led by founders with track records at Meta, SpaceX, Epirus, and the U.S. Department of Defense.

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Responsibilities:

• Design, characterize, and deliver algorithms such as channelizers, frequency agile detection, adaptive filters, MIMO, wideband detectors, and other algorithms related to signal sorting
• Write and contribute to existing Python repositories using CUDA and PyTorch
• Own requirements, ICDs, and verification from concept through delivery
• Stay current: Track and insert advances in signal processing techniques and associated technologies, adaptive beamforming, RF machine learning, and resilient PNT for GPS-denied ops.

Required Qualifications:

• Masters Degree in Electrical, Computer or Systems Engineering or related field with Graduate study emphasis in Signal Processing; OR a Bachelor’s Degree in an Engineering discipline with 3-5 years relevant working Signal Processing Experience
• Intermediate to advanced proficiency in Python
• Willingness to support critical test events that occasionally require extended hours/weekends.
• Ability to obtain and maintain a security clearance. Learn more about Security Clearances here.
• Must be a U.S. Person (see ITAR Regulations below) due to required access to U.S. export-controlled information or facilities

Bonus Points:

• PhD in Electrical Engineering, Computer Engineering, or related field
• 5+ years’ experience with EW subsystems and payloads.
• EA/ECM technique design (deception, Digital RF Memory, coherent/non-coherent techniques).
• Comms system design (LPI/LPD, Waveform-of-Interest exploitation)
• RF machine learning for emitter ID, modulation/classification, anomaly detection, PDW creation
• Tools Experience: ADS/AWR/SystemVue, MATLAB/Simulink, Python (NumPy/SciPy), GNU Radio/SDR (USRP/RFSoC), VITA-49; HDL/firmware experience also helpful (Vivado/Quartus/Libero).
• Clearance: Active Secret or ability to obtain and maintain; TS/SCI eligibility preferred. ITAR/EAR-controlled work.
• Field work: supporting periodic travel for flight tests and customer demonstrations/support
• Mindset: Builder-tester who loves first-principles RF, rapid lab iteration, and getting hardware flying fast.

What We Offer:

• Competitive salary, stock options and benefits, including health, vision and dental.
• 401K enrollment at 90 days.
• Generous PTO + most Federal Holidays observed.
• Collaborative and inclusive work environment.
• Access to the latest tools and technologies.
• High levels of responsibility and autonomy.
• Professional growth and development opportunities.
• Access to the hardest problems in electronic warfare.

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This role requires an onsite presence in our El Segundo, CA HQ; a remote work environment is not considered for this opportunity.

Key Responsibilities:

• Design, validate & deliver RF payload subsystems: Design, Integration and Testing of Antennas, RF front ends, SDRs and provide validation of operation. Support development and analysis of RF performance metrics.

• Own requirements, ICDs, and verification from concept through delivery

• Stay current: Track and insert advances in relevant technologies, SDRs, RF Systems, RF machine learning, and PNT.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, or related field

• Antenna and receiver design across analog/RF/mixed-signal domains: mixers, PLLs/LOs, gain/linearity/noise trades; ability to turn simulations into reality.

• Channelizers & wideband architectures: filter banks, analog/digital down conversion, sample-rate planning, clocking/synchronization.

• Willingness to support critical test events that occasionally require extended hours/weekends

• Ability to obtain and maintain a security clearance

• Must be a U.S. Person (see ITAR Regulations below) due to required access to U.S. export-controlled information or facilities

Bonus Points:

• PhD in Electrical Engineering, Computer Engineering, or related field

• 5+ years’ experience with EW subsystems and payloads

• EA/ECM technique design (deception, Digital RF Memory, coherent/non-coherent techniques)

• Digital Signal processing: Design characterize and deliver channelizers, wideband detection/classification, MIMO/digital-arrays, and algorithms in MATLAB/Python/C++

• Communication / Waveform system design

• RF machine learning for emitter ID, modulation/classification, anomaly detection, PDW creation

• Tools Experience: ADS/AWR/SystemVue, MATLAB/Simulink, Python (NumPy/SciPy), GNU Radio/SDR (USRP/RFSoC), VITA-49; HDL/firmware experience; also helpful (Vivado/Quartus/Libero).

• Clearance: Active Secret or ability to obtain and maintain; TS/SCI eligibility preferred. ITAR/EAR-controlled work. Learn more about Security Clearances here.

• Field work: supporting periodic travel for flight tests and customer demonstrations/support

• Mindset: Builder-tester who loves first-principles RF, rapid lab iteration, and getting hardware flying fast

What We Offer:

• Competitive salary, stock options and benefits, including health, vision and dental.

• 401K enrollment at 90 days.

• Generous PTO + most Federal Holidays observed.

• Collaborative and inclusive work environment.

• Access to the latest tools and technologies.

• High levels of responsibility and autonomy.

• Professional growth and development opportunities.

• Access to the hardest problems in electronic warfare.

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As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a High Frequency Electromagnetics Application Engineer, you will be part of the Electronics High Frequency team within the Ansys Customer Excellence group. This team is comprised of experts in RF, signal integrity, and simulation technologies, working collaboratively across disciplines and regions to deliver innovative solutions.

Your primary responsibilities will include:

• Leading and assisting in coordinating technical activities throughout the sales opportunity lifecycle, including technical discovery, product presentations, demonstrations, and evaluations.
• Providing best-in-class solutions involving RF, antenna flows, and PCB/system interactions for signal and power integrity flows, EMI/EMC, collaborating across regions and functions.
• Participating in external and internal events to enhance RF/SI/PI/EMI simulation solutions and contribute to professional growth and marketing efforts.
• Acting as a product expert for Ansys products, engaging with customers to understand their design needs and workflows, highlighting Ansys' value proposition.
• Working closely with product development teams to translate customer requirements into innovative product features and test new releases on industrial problems.
• Delivering consulting services and conducting introductory or intermediate training classes to empower customers and colleagues.

In this role, you will drive customer success by integrating advanced simulation tools into their engineering workflows, enabling efficient and accurate design outcomes. You will also enhance Synopsys' reputation for technical excellence and customer-centric innovation through tailored solution delivery.

Requirements:

• MS/PhD in Electrical/Electronic Engineering or equivalent, with specialization in electromagnetics.
• 5–7 years of experience in the high-frequency domain, using simulation tools for real-world applications.
• Expertise with Ansys HFSS, SIwave, Q3D Extractor, or comparable industry simulation software.
• Understanding of high-frequency, microwave, and antenna concepts, including S-parameters, wave propagation, and radiation patterns.
• Ability to research, debug, and resolve software-related issues efficiently.

Preferred qualifications include familiarity with signal and power integrity simulation, experience building automation workflows for RF/Signal/Power Integrity/EMC simulation flows, knowledge of commercial packages such as ADS, SystemVue, Simulink, AWR, CST, FEKO, and awareness of 5G systems, phased array, digital beamforming, microwave components, communication, and radar systems.

If you are a logical problem-solver with strong interpersonal and communication skills, highly organized and adept at time management, professional, business-oriented, and driven to succeed in fast-paced environments, we encourage you to apply.

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This role is for a Pre-Silicon Signoff Lead who will be responsible for leading simulation and sign-off activities that guarantee reliability and performance. The ideal candidate will have a rich background in high-speed serial communication and advanced transceiver design, with expertise in theoretical modeling and hands-on lab work.

Key responsibilities include collaborating closely with analog, digital, and hardware teams to ensure comprehensive design and verification coverage, developing and maintaining robust simulation and verification plans for IP, and reviewing progress against verification plans through regular meetings with multiple verification teams.

The successful candidate will have a strong command of simulation, verification, and hardware validation processes, with experience in high-speed protocols such as PCIe and Ethernet. They will also have a proven track record of leadership in testbench architecture, planning, cross-site collaboration, and mentoring.

As a member of our world-class engineering team, you will drive innovation, tackle complex challenges, and ensure our products empower customers to achieve their goals in enterprise, data center, and networking applications.

If you are an innovative and forward-thinking engineer with a passion for advancing connectivity technologies, we encourage you to apply for this exciting opportunity.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and passionate ASIC Digital Design Engineer who thrives in dynamic and collaborative environments. You have a proven track record in RTL design and verification, and you are excited about contributing to cutting-edge technology. With your extensive expertise, you can handle complex and unique issues, often requiring innovative solutions. You are adept at communicating with both internal and external stakeholders, ensuring that your designs meet the highest standards of quality and performance.

What You’ll Be Doing:

• Leading the design and verification of complex ASIC blocks and systems, ensuring they meet all specifications and performance goals.
• Collaborating closely with cross-functional teams, including analog design, physical design, and applications engineering, to ensure seamless integration of all design components.
• Developing and executing comprehensive test plans to verify the functionality and performance of your designs.
• Utilizing advanced EDA tools and methodologies to optimize design performance and power efficiency.
• Mentoring junior engineers, providing guidance and support to help them grow their skills and contribute effectively to the team.
• Staying up to date with the latest industry trends and technologies, continuously improving your skills and knowledge.

The Impact You Will Have:

• Driving innovation in ASIC design, contributing to the development of cutting-edge technology that shapes the future.
• Ensuring the delivery of high-performance, reliable, and power-efficient ASICs that meet customer requirements and industry standards.
• Enhancing the overall quality and performance of Synopsys' products through meticulous design and verification processes.
• Collaborating with cross-functional teams to solve complex design challenges, ensuring seamless integration and functionality.
• Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement within the team.
• Contributing to Synopsys' reputation as a leader in the semiconductor industry through your expertise and innovative solutions.

What You’ll Need:

• Extensive experience in ASIC digital design and verification, with a strong background in RTL design, using industry standard HDLs; Verilog, SystemVerilog.
• Proficiency in using industry-standard EDA tools and methodologies for design and verification.
• Deep understanding of High-Performance Interface IP protocols and their implementation in ASIC design, such as PCIe, CXL, DDR, Ethernet, AMBA (CHI, AXI, AHB, APB).
• Broad knowledge of the full digital ASIC and IP development flow, including RTL design, lint, CDC, RDC, synthesis and STA.
• Experience with power analysis and RTL level power optimization techniques.
• Familiarity with verification languages and methodologies; SystemVerilog, SVA, UVM.
• Strong analytical and problem-solving skills, with the ability to tackle complex and unique design challenges.
• Excellent communication skills, with the ability to effectively collaborate with cross-functional teams and stakeholders.

Who You Are:

• A proactive and self-motivated individual who takes initiative and acts independently with minimal oversight.
• A strategic thinker with the ability to implement goals that have a direct impact on department results.
• A detail-oriented engineer who works meticulously to ensure the highest standards of quality and performance.
• A collaborative team player who thrives in dynamic and fast-paced environments.
• A lifelong learner who stays up to date with the latest industry trends and continuously seeks to improve their skills and knowledge.

The Team You’ll Be A Part Of:

You will be part of a highly skilled and dynamic ASIC Digital Design team focused on delivering high-performance and reliable ASIC solutions. Our team collaborates closely with various departments, including analog design, physical design, and applications engineering, to ensure the seamless integration of all design components. We are committed to continuous learning and improvement, fostering a culture of innovation and excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Your responsibilities will include designing, configuring, deploying, monitoring, and troubleshooting production network infrastructure and associated services, including LAN, WAN, Data Center, remote access, wireless, and firewall security. You will develop and maintain comprehensive documentation for network configurations, processes, security policies, and procedures.

You will define and lead networking strategy aligned with business growth, automation goals, and scalable AI infrastructure. You will implement automation tools and AI-driven solutions to optimize network operations and reduce manual intervention. You will utilize automation tools to standardize deployment configurations and environments for consistency and efficiency.

You will identify and resolve issues related to network and security infrastructure performance, efficiency, and availability. You will communicate effectively with stakeholders at all levels, translating complex technical topics into accessible insights.

As a Sr. Staff Network Engineer, you will enable secure, scalable, and highly available network infrastructure supporting Synopsys' global business operations. You will drive innovation through the adoption of automation and AI, enhancing network efficiency and reducing manual overhead. You will champion best practices and standards that elevate network reliability, security, and performance.

You will mentor and empower team members, fostering a culture of learning, collaboration, and technical excellence. You will contribute to strategic initiatives that align networking capabilities with company growth and emerging technologies. You will enhance stakeholder engagement through clear communication and the delivery of impactful solutions.

You will influence the direction of Synopsys' network architecture, ensuring it remains at the forefront of industry advancements.

To be successful in this role, you will need:

• Bachelor's degree in Computer Science, Information Technology, Engineering, or related field
• 8+ years of experience in network engineering, with several years in senior staff or architecture-oriented roles
• Expertise in designing and supporting large-scale enterprise networks
• Deep understanding of network security systems and protocols (IPSec, IKE, GRE, TACACS, RADIUS, 802.1x, NAC, EAP-TLS)
• Expert-level knowledge of networking fundamentals: TCP/IP, switching/routing, BGP, OSPF, DMVPN, EVPN/VXLAN, SD-WAN, MPLS
• Proficiency in wireless standards and technologies: 802.11a/b/g/n/ac/ax, MIMO, beamforming, channel planning
• Experience with network configuration management and automation tools (Python, Ansible, OpenStack, Terraform, REST API)
• Extensive hands-on experience with Cisco, Aruba, Zscaler, Palo Alto Networks equipment and platforms
• Ability to analyze raw packet data to uncover network performance issues (latency, packet loss, application errors)
• Ability to work after hours for project and maintenance needs
• Program management skills to align cross-functional teams and drive results
• Understanding of AI, machine learning, LLMs, MCP technologies
• Relevant certifications (PCNSE, ZIA/ZPA, CCNP, CCDP, CCIE, CISSP, CCDE, CEH, Security+ or equivalent experience) are a plus

As a Sr. Staff Network Engineer, you will be a forward-thinking and innovative individual, always seeking to improve and streamline processes. You will be a collaborative leader and mentor, passionate about empowering others and sharing expertise. You will be an excellent communicator, able to bridge technical and non-technical audiences. You will be adaptable and resilient, thriving in dynamic environments. You will be strategic and detail-oriented, balancing big-picture vision with hands-on execution. You will be committed to integrity, excellence, leadership, and passion,core Synopsys values.

You will join a dynamic global network engineering team responsible for designing and supporting all network services,including LAN, WAN, Data Center, remote access, wireless, and firewall security. This collaborative group is focused on delivering secure, scalable, and resilient network solutions, embracing automation and AI to drive continuous improvement. As a mentor and leader, you will help shape a culture of innovation and learning within the team.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Your key responsibilities will include working in a Digital and Verification Development team during the development and validation of complex digital mixed signals for high-speed interface IP. You will plan tests, checklists, coverage, and assertion planning. You will create detailed verification environments from functional specifications. You will apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. You will write test cases, checkers, and coverage that implement the verification test plan. You will debug simulations, including those of real signals modeled using SystemVerilog for analog. You will perform RTL, GLS, and co-simulations and ensure coverage closure. You will participate in technical reviews and contribute actively. You will provide customer support with the bring-up of IP in customer simulation environments. You will follow and improve development processes to ensure high-quality output.

To be successful in this role, you will need a BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. You will require 2+ years of experience in design verification. You will need strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. You will require proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

As a highly responsible and result-oriented individual, you will excel in this role if you have excellent English communication skills, both verbal and written. You will be a great team player, willing to support others. You will be self-motivated and highly enthusiastic about technology and solving problems.

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At Synopsys, we value diversity and inclusion. We are committed to creating a workplace where everyone feels valued and supported to do their best work.

Responsibilities: Assist SiCADA instructor in developing VDM (Verilog Design Methodology) & ADV (Advanced Design Verification) homework specifications. Assist in reviewing ADV course materials, including SVTB (SystemVerilog Testbench) and UVM (Universal Verification Methodology), and update the course content. Serve as a teaching assistant for the VDM and ADV courses, helping to answer student questions and grade assignments. Support SoC implementation course especially STA and UPF teaching assistance if possible.

Benefits: Professional development opportunities Collaborative and dynamic work environment Flexible work arrangements

Hiring Journey at Synopsys: Apply Phone Screen Interview Offer Onboarding Welcome!

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Your responsibilities will include:

• Architecting and optimizing high-performance simulation kernels for the Synopsys VCS RTL simulator using advanced C++ techniques.
• Exploring and implementing GPU acceleration strategies with CUDA to significantly reduce simulation runtimes for customers.
• Leveraging deep knowledge of Verilog/SystemVerilog LRM to ensure accurate and reliable simulation across diverse design environments.
• Integrating AI-powered tools (such as Cursor, GitHub Copilot, and generative AI assistants) to automate code generation and debugging processes.
• Mentoring and guiding junior engineers, fostering skills development and technical growth within the team.
• Collaborating with distributed R&D teams to maintain Synopsys' leadership and drive innovation in the EDA industry.

As a senior staff engineer, you will have a significant impact on the company's success. You will be responsible for driving the evolution of the world's fastest Verilog simulator, setting new industry standards for performance and reliability. You will also empower customers to achieve greater productivity and efficiency through advanced simulation capabilities and reduced runtimes.

To be successful in this role, you will need to have:

• 8-10 years of relevant experience.
• Expert-level proficiency in C++ with proven experience in performance-critical software development.
• Deep understanding of Verilog/SystemVerilog Language Reference Manuals (LRM) and simulation methodologies.
• Hands-on experience with GPU programming, especially using CUDA for parallel acceleration.
• Familiarity with AI-powered development tools such as Cursor, GitHub Copilot, and generative AI assistants.
• Strong architectural design skills and ability to analyze and optimize complex software systems.
• Experience in mentoring and guiding junior engineers within an R&D environment.

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You will work closely with customers, Sales, R&D, and field teams to help them adopt and deploy Synopsys Verification solutions.

Responsibilities

• Engage directly with customers to understand their verification needs
• Support pre-sales activities: demos, technical evaluations, benchmarks, methodology guidance
• Improve customer verification flows and testbench architectures
• Debug RTL/gate-level simulation issues and SystemVerilog/UVM environments
• Analyse functional and code coverage
• Develop and debug SystemVerilog assertions
• Collaborate with Sales to grow adoption and identify new opportunities
• Act as the technical voice of the customer to R&D

Requirements

• Typically requires 8–13 years of relevant experience
• Strong knowledge of Verilog/SystemVerilog, UVM, coverage, and assertions
• Experience in customer interaction, pre-sales, or technical support is a plus
• Strong problem-solving and communication skills
• Bachelor’s degree in Computer Engineering, Electrical Engineering, or related field

The Team You’ll Be A Part Of

You’ll join a dynamic, Theale based Customer Application Services team dedicated to delivering world-class technical support and solutions for leading semiconductor companies.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a global leader in semiconductor design and verification solutions, we enable the world's most advanced technology companies to deliver cutting-edge SoCs and systems. Our mission is to accelerate innovation through state-of-the-art verification IP, methodologies, and strategic consulting.

You are a passionate and analytical engineer with a proven track record in digital design and verification, ready to embrace the challenge of developing advanced embedded memory test and SLM architectures. You thrive in dynamic, collaborative environments where your technical expertise and innovative mindset can drive significant impact.

You are detail-oriented, always seeking to ensure design integrity and optimal performance through rigorous validation, debugging, and synthesis. Your hands-on approach extends to scripting and automation, enhancing productivity and accelerating development cycles. You communicate effectively with cross-functional teams, translating complex technical concepts for diverse stakeholders, and you enjoy mentoring and guiding others to achieve shared goals.

Developing and modeling RTL logic in Verilog for embedded memory test and SLM IP blocks. Performing digital design validation and functional verification at both block and SoC levels. Executing logic synthesis, static timing analysis, and generating fault coverage reports to ensure robust designs. Applying DFT (Design-for-Test) expertise for comprehensive memory and logic testing. Identifying and troubleshooting design timing and DFT functional issues to optimize chip performance. Utilizing and scripting in languages such as Tcl to automate design and verification workflows. Developing and maintaining technical collateral including test suites, protocol documentation, and debug guides.

Accelerate the delivery of reliable, high-performance SoCs for industry-leading technology companies. Shape the evolution of embedded memory test and SLM architectures that power next-generation devices. Drive innovation in simulation, emulation, and verification methodologies for advanced semiconductor products. Enhance customer satisfaction by delivering robust, easy-to-use IP and responsive technical support. Contribute to the continuous improvement of Synopsys' design and verification solutions, setting new industry benchmarks. Mentor and elevate team capabilities, fostering a culture of excellence, knowledge sharing, and mutual growth. Influence the adoption of best practices in DFT, protocol compliance, and subsystem integration across the organization. Support strategic decision-making by providing technical insights and market-driven recommendations.

2-4 years of relevant experience in ASIC digital design and verification. Proficiency in RTL simulation, logic synthesis, and timing verification tools. Strong understanding of DFT architectures. Familiarity with debug tools such as Verdi and workflows for performance analysis. Programming skills in SystemVerilog, UVM, Verilog, C/C++, Python, and scripting languages like Tcl. Experience with EDA tools such as VCS, Verdi, and DC, and methodologies including VC Auto-Testbench and protocol compliance checking.

Analytical thinker with exceptional problem-solving skills. Effective communicator, able to collaborate across disciplines and with external partners. Proactive, self-motivated, and adaptable in fast-paced environments. Committed to quality, detail, and continuous learning. Team player who values diversity, inclusion, and mentorship. Customer-focused, dedicated to delivering timely and effective solutions.

You'll join a highly collaborative and innovative team of digital design and verification experts, working at the forefront of embedded memory test and SLM architecture development. The team bridges R&D, marketing, and customer engagement, driving the roadmap for advanced SoC solutions. With a culture of knowledge sharing, technical excellence, and mutual support, you'll thrive in an environment that values creativity, initiative, and a shared commitment to shaping the future of semiconductor technology.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Description

Date posted: 03/29/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a forward-thinking engineer with a passion for leveraging cutting-edge AI technologies to revolutionize electronic design automation and verification. You thrive in dynamic environments where innovation, collaboration, and continuous learning are valued. Your experience in verification frontend flows and AI/ML frameworks enables you to bridge the gap between traditional engineering practices and intelligent automation. You are comfortable working across diverse teams, collaborating with design, verification, CAD, and methodology experts to identify impactful automation opportunities. You possess strong analytical skills, enabling you to dissect complex verification challenges and develop scalable GenAI solutions. Your commitment to professional growth is evident in your eagerness to stay current with the latest advancements in LLMs, GenAI, and verification technology. With a keen eye for detail and a drive to deliver high-quality results, you are adept at integrating AI-driven capabilities into established workflows, elevating productivity and efficiency. You value inclusivity and diverse perspectives, and you are motivated by the opportunity to shape the future of engineering through innovative, intelligent solutions.

What You’ll Be Doing:

• Develop and deploy LLM/GenAI-based solutions to enhance verification productivity across static, formal, and simulation-based flows in EDA tools.

• Collaborate cross-functionally with design, verification, CAD, and methodology teams to identify high-impact areas for AI-assisted automation.

• Build tools and frameworks to generate or refine assertions, constraints, checkers, and test intent, summarize design/spec content, and analyze logs, failures, and coverage gaps.

• Integrate LLM-driven capabilities into existing verification flows, tools, and automation infrastructure, ensuring seamless adoption.

• Develop and maintain scripts, data pipelines, and evaluation frameworks for AI-assisted verification use cases.

• Stay current with advances in LLMs, GenAI, verification technology, and digital design methodologies to inform best practices.

• Participate in technical reviews and help define scalable AI adoption strategies within verification environments.

The Impact You Will Have:

• Accelerate verification planning, setup, and closure, enabling faster time-to-market for complex digital designs.

• Enhance productivity and efficiency for engineering teams through intelligent automation and AI-driven solutions.

• Reduce manual effort and potential errors in verification by automating routine and complex tasks.

• Improve coverage analysis, debug processes, and testbench/content generation, resulting in higher quality silicon chips.

• Drive innovation in verification methodologies by integrating state-of-the-art GenAI capabilities.

• Foster cross-functional collaboration, contributing to robust and scalable verification strategies.

• Support Synopsys’ leadership in EDA technology and AI-driven engineering solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.

• 5–8 years of experience in EDA software development with prior experience in developing GenAI-based tools.

• Hands-on experience with LLM/GenAI or AI/ML frameworks/tools such as PyTorch, TensorFlow, Hugging Face, LangChain, or equivalent.

• Proficiency in C++ and familiarity with Verilog, VHDL, or SystemVerilog.

• Strong understanding of verification frontend methodologies, including static analysis (CDC/RDC/Lint), formal/property-based verification, and simulation bring-up/debug.

• Experience with cloud or scalable compute platforms (AWS, GCP, Azure) is a plus.

• Familiarity with Agile development methodologies is desirable.

Who You Are:

• Innovative thinker with a passion for applying AI to real-world engineering challenges.

• Effective communicator, able to convey complex technical concepts to diverse audiences.

• Collaborative team player who thrives in cross-functional environments.

• Strong problem-solving abilities and analytical mindset.

• Adaptable, eager to learn, and comfortable with ambiguity in fast-evolving technology landscapes.

• Self-driven and proactive, with a commitment to delivering impactful solutions.

The Team You’ll Be A Part Of:

You will join a collaborative and innovative engineering team focused on advancing verification productivity through AI-driven solutions. The team works closely with design, verification, CAD, and methodology groups to identify and implement high-impact automation strategies. Together, you will drive the adoption of GenAI technologies within Synopsys’ EDA ecosystem, fostering a culture of continuous improvement and technological excellence.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You have a strong passion for working with embedded processors or processor-based systems.

You bring knowledge of HDL design, with a preference for experience in RISC processor architectures, DSP, AI (Neural Processing Unit), and multi-core systems.

You are familiar with design and verification languages such as Verilog and SystemVerilog, and have experience with RTL simulation tools, such as VCS.

Scripting or programming skills in languages such as assembler, C, Tcl, Csh, and Python is desirable.

Experience with embedded software related to DSP or AI reference models is a plus.

You have strong analytical and problem-solving abilities, as well as excellent written and verbal communication skills, including proficiency in English, detailed status reporting, and the ability to present results to program management teams.

What You’ll Be Doing:

• Develop and maintain microprocessor hardware IP including specification, implementation, verification, and FPGA validation, with an emphasis on validating system architecture and performance for DSP processor IP or Neural Processing Unit (NPU) IP.

• Optimize designs for performance, area, and power efficiency.

• Create and enhance tests for hardware IP verification and validation, improving functional coverage and performance through the application of state-of-the-art methodologies.

• Collaborate with global teams in tools, modeling, and simulation to deliver optimized solutions for our customers.

The Impact You Will Have:

• Contribute to the development of highly optimized hardware IP for the ARC family of configurable processors.

• Enable customers to create sophisticated and efficient embedded designs.

• Support the delivery of world-class microprocessors used in advanced applications.

• Help improve functional coverage and performance of processor IP through advanced verification methods.

• Collaborate globally to deliver customer-focused solutions.

• Drive continuous improvement in processor system verification.

What You’ll Need:

• Passion for embedded processors or processor-based systems.

• Knowledge of HDL design, preferably in RISC processor architectures, DSP, AI (NPU), and multi-core systems.

• Familiarity with Verilog and SystemVerilog.

• Experience with RTL simulation tools (e.g., VCS).

• Scripting or programming skills in assembler, C, Tcl, Csh, or Python.

• Experience with embedded software for DSP or AI reference models is a plus.

Who You Are:

• Strong analytical and problem-solving abilities.

• Excellent written and verbal communication skills.

• Proficient in English.

• Capable of detailed status reporting and presenting results to program management teams.

The Team You’ll Be A Part Of:

Join our dynamic team dedicated to developing highly optimized hardware IP for the ARC family of configurable processors, enabling customers to create sophisticated and efficient embedded designs.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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As a Digital Verification Sr Engineer, you will be responsible for working in a collaborative environment to develop and validate complex digital mixed signals for high-speed interface IP.

Key responsibilities include: Planning tests, checklists, coverage, and assertion planning. Creating detailed verification environments from functional specifications. Applying advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification. Writing test cases, checkers, and coverage that implement the verification test plan. Debugging simulations, including those of real signals modeled using SystemVerilog for analog. Performing RTL, GLS, and co-simulations and ensuring coverage closure. Participating in technical reviews and contributing actively. Providing customer support with the bring-up of IP in customer simulation environments. Following and improving development processes to ensure high-quality output.

Requirements include: BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications. 2+ years of experience in design verification. Strong skills with VCS/Verdi simulation tools and formal verification tools (vc_formal). Knowledge of UPF, UVM (Universal Verification Methodology), and SVA (SystemVerilog Assertion) is a plus. Proficiency in debugging and demonstrated experience in Perl/TCL/Python scripting is a plus.

Ideal candidate will be highly responsible and result-oriented, with excellent English communication skills, both verbal and written. A great team player, willing to support others. Self-motivated and highly enthusiastic about technology and solving problems.

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As an experienced and visionary ASIC digital design architect, you will thrive in a fast-paced, collaborative environment. You will bring a passion for solving complex system-level challenges and a track record of delivering innovative, high-quality silicon solutions.

Your deep understanding of IP and SoC architectures enables you to see the big picture while meticulously refining subsystem details. You are comfortable navigating ambiguity, building consensus across diverse teams, and translating product requirements into robust, scalable architectures.

Your leadership inspires those around you, and you excel at mentoring and empowering engineers to reach their full potential. You are adept at balancing trade-offs across performance, power, area, and security, always striving for the optimal solution.

Communication is your strength,you articulate technical concepts clearly to both technical and non-technical stakeholders, ensuring alignment and shared understanding.

With a growth mindset, you embrace new challenges, technologies, and methodologies, continuously seeking opportunities to innovate and improve.

You value inclusion and diversity, recognizing that the best ideas emerge from a culture where everyone feels empowered to contribute.

As an IP Subsystems Architect, you will define architectural specifications for complex subsystems, translate system-level requirements into detailed subsystem architectures, and integrate multiple IP blocks into cohesive subsystems.

You will lead cross-functional collaboration with hardware, software, verification, and physical design teams to ensure subsystem feasibility and correctness.

Establishing and guiding verification and validation strategies, including defining coverage requirements and participating in silicon bring-up and debug sessions.

Producing comprehensive architecture documents, specifications, and guidelines, and clearly communicating architectural intent to a wide range of stakeholders.

Mentoring and coaching engineers, driving best practices, and fostering a culture of technical excellence.

Shape the architecture of industry-leading silicon IP and subsystem solutions that power millions of devices worldwide.

Accelerate time-to-market for differentiated products by ensuring robust and efficient subsystem design and integration.

Reduce risk through rigorous requirements management, architectural clarity, and cross-functional alignment.

Enhance product performance, power efficiency, and reliability, directly impacting customer satisfaction and competitive advantage.

Foster innovation by mentoring teams, introducing new methodologies, and championing best practices.

Strengthen Synopsys’ position as a trusted technology leader in the semiconductor ecosystem.

Bachelor’s or Master’s degree in Electronics or a related field, with 15+ years of industry experience.

At least 10 years in semiconductor design, IP integration, or SoC/subsystem architecture roles.

Deep expertise in Verilog/SystemVerilog, simulation tools, and advanced verification methodologies (e.g., SV UVM, BFM development).

Proficiency with industry-standard interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.).

Experience with synthesis, lint, CDC, low-power flows, and achieving verification closure.

Strong documentation and communication skills for effective cross-team alignment and requirements management.

A strategic thinker with exceptional leadership and mentoring capabilities.

A collaborative partner who thrives in diverse, cross-functional teams.

An excellent communicator, able to tailor messaging for both technical and non-technical audiences.

Innovative and proactive, always seeking opportunities to improve processes and outcomes.

Resilient and adaptable, comfortable with change and ambiguity.

Committed to fostering an inclusive and empowering team culture.

Join the Digital IP Subsystems Team at Synopsys,a high-performing group of architects, designers, and engineers focused on delivering world-class silicon IP and subsystem solutions.

The team collaborates closely with hardware, software, verification, and product teams across the globe, driving innovation in next-generation SoCs for AI, automotive, 5G, IoT, and more.

Together, we value creativity, technical excellence, and inclusion, empowering each team member to make a significant impact.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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As a Sr Staff Application Engineer - VCS Simulation, you will be responsible for leading customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.

Responsibilities

• Lead customer deployments of VCS simulation technology, working closely with field teams and R&D to ensure successful adoption and integration.
• Diagnose and troubleshoot complex technical issues in verification flows, utilizing deep product knowledge and analytical skills.
• Collaborate with global domain experts to gather requirements and contribute to the development of a robust product roadmap.
• Drive competitive engagements by demonstrating Synopsys VCS advantages and supporting customers in benchmarking scenarios.
• Provide technical expertise in HDL/HVL methodologies, including UVM, SVA, and simulation debugging.
• Interface directly with customers, product validation, and R&D teams to propose solutions and suggest improvements in implementation and validation processes.
• Develop and optimize scripts (Perl, TCL, Shell, Make) to enhance productivity and workflow automation.

The Impact You Will Have

• Enable customers to accelerate their verification cycles and achieve first-pass silicon success through expert support and deployment of VCS simulation technology.
• Drive innovation in verification methodologies by integrating advanced features and AI-driven productivity tools.
• Enhance Synopsys' product offerings by providing actionable feedback from customer engagements and competitive benchmarking.
• Facilitate seamless collaboration across global teams, ensuring consistent delivery of high-quality solutions.
• Support the continuous improvement of VCS and related technologies through proactive problem-solving and technical leadership.
• Contribute to the growth of Synopsys' leadership in EDA by empowering customers to leverage the full capabilities of verification platforms.

What You’ll Need

• Bachelor’s degree in Electronics with 7+ years or Master’s degree in Electronics with 5+ years of experience.
• Proficiency in verification technologies, including simulation, UVM, SVA, and LRM.
• Strong expertise in HDL languages (Verilog, VHDL, SystemVerilog) and digital design fundamentals.
• Proven experience in debugging simulation mismatches and verification flows.
• Advanced scripting skills (Perl, TCL, Make, Shell) and working knowledge of UNIX environments.
• Exposure to Synopsys EDA tools such as SpyGlass, VC SpyGlass, Verdi is a plus.

Who You Are

• Excellent written and oral communication skills, comfortable interfacing with global teams and customers.
• Collaborative team player with a proactive and innovative mindset.
• Detail-oriented and organized, able to manage multiple tasks and priorities.
• Motivated self-starter with strong problem-solving abilities.
• Adaptable and open to travel, eager to learn and grow in a fast-paced environment.

The Team You’ll Be A Part Of

You will join a dynamic and diverse team of applications engineers dedicated to solving the most challenging problems in the verification domain. Our team works at the intersection of technology development, customer engagement, and product innovation, collaborating with experts across field, R&D, and product validation globally. We foster a culture of continuous learning, open communication, and mutual support, ensuring every member can make a meaningful impact and grow professionally.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You have a proven track record in digital design and verification, and you are comfortable working across ASIC, FPGA, and firmware domains. Your experience enables you to interpret and review digital and analog specifications, create robust analog models, and write modular, constrained-random testbenches in Verilog and SystemVerilog.

You are adept at performing functional, assertion, and code coverage, and you have a keen eye for failure analysis and testplan management. Your organisational skills ensure that projects move forward efficiently, and your communication abilities allow you to interface effectively with multidisciplinary teams and customer support groups.

You value diversity, inclusivity, and continuous learning, seeking out opportunities to grow and mentor others. As someone who is motivated by innovation, you are excited to work with an expert team and help deliver high-end mixed-signal designs that power the next generation of smart technology.

Responsibilities:

• Designing and verifying ASIC, FPGA, and firmware for high-speed mixed-signal circuits.

• Reviewing digital and analog specifications to ensure alignment with project goals.

• Creating analog models based on schematics and functional requirements.

• Developing modular, constrained-random testbenches in Verilog and SystemVerilog for robust verification.

• Performing functional, assertion, and code coverage, analysing results to identify areas for improvement.

• Developing, managing, and tracking comprehensive testplans to ensure thorough verification.

• Reviewing and analysing failure cases to drive corrective actions and enhance product reliability.

• Running gate-level simulations to validate design integrity and performance.

• Collaborating with cross-functional design groups and customer support teams to resolve technical challenges.

Impact:

• Advancing the development of high-performance mixed-signal designs that enable next-generation applications.

• Ensuring functional and performance integrity of silicon IP products through rigorous verification.

• Accelerating time-to-market for differentiated products by reducing risk and increasing design confidence.

• Contributing to the world's broadest portfolio of silicon IP, supporting innovation in AI, IoT, 5G, and more.

• Enhancing reliability and quality of products that power smart devices and autonomous systems.

• Supporting Synopsys' reputation as a leader in chip design and software security by delivering excellence.

Requirements:

• BSEE with 2 years of digital design and verification experience, or MSEE with 0 years of digital design and verification industry experience.

• Expertise in ASIC design, synthesis, and clock domain crossing (CDC).

• Hands-on experience writing complex testcases in Verilog and SystemVerilog.

• Familiarity with code quality metrics and best practices in verification methodologies.

• Ability to create system-level specifications for digital and analog domains.

• Strong knowledge of high-speed digital and mixed-signal design principles.

• Experience with asynchronous clock crossings and DFT (Design For Test) methodologies.

Team:

Join a highly experienced mixed-signal design team, dedicated to delivering high-end mixed-signal designs from specification development through functional and performance testing. You'll be working alongside expert digital and mixed-signal engineers, collaborating across design, verification, and customer support to push the boundaries of innovation in silicon IP and SoC integration.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a passionate Computer Scientist with an exceptional analytical mind, driven by curiosity and a desire to solve some of the most challenging problems in automated logical reasoning and symbolic computation. You thrive in intellectually stimulating environments, enjoying the pursuit of innovative solutions within deep technology domains. Your expertise spans formal methods, algorithms, and complexity theory, enabling you to tackle large-scale, industrial verification challenges with confidence and creativity.

You bring hands-on experience in developing robust software solutions, particularly in C/C++. Whether your background is academic or industry, your contributions have been recognized by peers, and you are eager to collaborate with leading experts in the field. You understand the nuances of hardware architecture and design languages like SystemVerilog, or you are enthusiastic to learn them, appreciating their impact on verification excellence.

You are adaptable, open to new ideas, and motivated by continuous learning. You value diversity of thought, enjoy working in collaborative teams, and are committed to advancing the state of the art in formal verification. You believe in the transformative power of AI/ML-assisted design flows and are excited to shift the paradigm from design-centric to verification-centric innovation. Above all, you are ready to make a significant impact in the future of technology by joining the Synopsys Formal Technology Group.

Designing and implementing advanced formal verification algorithms and proof engines for large-scale VLSI chip designs. Developing scalable, memory-efficient, and mathematically robust solvers to address industry-leading verification challenges. Integrating innovative solutions into the Synopsys VC Formal platform, enhancing its capabilities and usability for thousands of engineers worldwide. Collaborating with cross-functional teams to extend formal verification technologies into domains such as hardware security, functional safety, and low power. Engaging with customers and industry partners to understand their verification needs and deliver best-in-class solutions. Contributing to the formal verification community through peer-reviewed publications, technical presentations, and mentorship of junior team members.

Advancing the scalability and reliability of formal verification tools used by leading chip design companies. Breaking complexity barriers, enabling verification of the most challenging and extensive industrial designs. Driving innovation in AI/ML-assisted design flows, transforming the verification landscape for the semiconductor industry. Empowering customers to achieve functional safety, hardware security, and low power goals in their products. Facilitating widespread adoption of formal methods across diverse domains and applications. Fostering a collaborative, intellectually rich environment that inspires continuous learning and knowledge sharing.

8-10 years of relevant experience Expertise in formal methods, model checking, theorem proving, and equivalence checking. Strong proficiency in algorithms, data structures, and complexity analysis. Professional coding skills in C/C++ and experience developing large-scale software systems. Background in hardware architecture and familiarity with design languages such as SystemVerilog (preferred but not required). Peer recognition in the formal verification community, such as publications or industry accolades.

Analytical thinker with a keen eye for detail and problem-solving. Collaborative team player who values diversity and open communication. Innovative and adaptable, willing to embrace new technologies and methodologies. Driven by curiosity and a passion for continuous learning. Resilient in the face of challenging technical problems and complexity.

You’ll join the Synopsys VC Formal R&D Team,a vibrant community of talent and expertise dedicated to advancing formal verification technologies. The team is renowned for solving deep theoretical and practical problems and integrating them into world-leading verification tools. You will collaborate with experts in formal methods, software engineering, and AI/ML, contributing to the proliferation of formal verification across hardware security, functional safety, low power, and more.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.

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We are seeking a seasoned engineer with a passion for pushing the boundaries of technology to join our team. With 5-8 years of experience, you will bring a wealth of knowledge in software architecture and excel in C/C++ software development, digital simulation, compiler optimizations, and design patterns, data structures, and algorithms.

As a member of our performance team in Digital Simulation, you will work closely with both local and global teams to drive technological advancements and achieve project goals.

Responsibilities:

• Designing, developing, and troubleshooting core algorithms for compiler.
• Collaborating with local and global teams to enhance runtime performance for verilog compiler.
• Engaging in pure technical roles focused on software development and architecture.
• Utilizing your knowledge of digital simulation flows and EDA tools to drive innovation.
• Leveraging your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.

Impact:

• Driving technological innovation in chip design and verification.
• Enhancing the performance and quality of simulation tools used globally.
• Solving complex compiler optimizations problems to improve simulation performance.
• Collaborating with cross-functional teams to achieve project milestones.
• Pioneering new software architectures that set industry standards.

Requirements:

• Strong hands-on experience in C/C++ based software development.
• Deep understanding of design patterns, data structures, algorithms, and programming concepts.
• Knowledge of ASIC design flow and EDA tools and methodologies.
• Proficiency in Verilog, SystemVerilog, and VHDL HDL.

Who You Are:

• Highly enthusiastic and energetic team player with excellent communication skills.
• Strong desire to learn and explore new technologies.
• Effective problem-solver with a keen analytical mind.
• Experienced in working on Unix/Linux platforms.
• Adept at using developer tools such as gdb and Valgrind.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Job Description

We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams - architecture, verification, physical implementation, and firmware - to deliver industry-leading SecurityIP solutions.

Responsibilities

• Leading a diverse team of design engineers in the development of next-generation SecurityIP solutions.
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Driving all phases of SecurityIP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth and a culture of innovation.
• Engaging with customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Impact

• Delivering industry-leading SecurityIP solutions that set new benchmarks for speed, bandwidth, and efficiency.
• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
• Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
• Enhancing product quality and reliability through rigorous design and verification processes.
• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, with 12-15 years of complex technical development experience.
• Minimum 2 years’ experience in people management and employee development.
• Proficiency in synthesizable Verilog and SystemVerilog design concepts and implementation.
• Strong background in front-end design flows: linting, synthesis, static timing analysis (STA), cross-domain clocking, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding of SecurityIP architecture is a plus.

Team

You’ll join the Synopsys SecurityIP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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We are seeking a seasoned engineer with a passion for pushing the boundaries of technology. With 6 - 15 years of experience, you bring a wealth of knowledge in software architecture. You excel in C/C++ software development, digital simulation, compiler optimizations and your strong background in design patterns, data structures, and algorithms sets you apart. Your expertise in Verilog, SystemVerilog, coupled with your experience in Unix/Linux platforms, makes you a valuable asset. You are well-versed in developer tools like gdb and Valgrind. Your analytical and problem-solving skills are top-notch, and you are always eager to learn and explore new technologies. As a highly enthusiastic and energetic team player, you are ready to go the extra mile to achieve success.

As a Principal Simulation R&D Software Engineer, you will be responsible for designing, developing, and troubleshooting core algorithms for compiler. You will collaborate with local and global teams to enhance runtime performance for verilog compiler. You will engage in pure technical roles focused on software development and architecture. You will utilize your knowledge of digital simulation flows and EDA tools to drive innovation. You will leverage your expertise in Verilog, SystemVerilog, and VHDL to develop cutting-edge solutions.

You will drive technological innovation in chip design and verification. You will enhance the performance and quality of simulation tools used globally. You will solve complex compiler optimizations problems to improve simulation performance. You will collaborate with cross-functional teams to achieve project milestones. You will pioneer new software architectures that set industry standards.

To succeed in this role, you will need strong hands-on experience in C/C++ based software development. You will require a deep understanding of design patterns, data structures, algorithms, and programming concepts. You will need knowledge of ASIC design flow and EDA tools and methodologies. You will require proficiency in Verilog, SystemVerilog, and VHDL HDL. You will need 10+ years of relevant EDA Software experience preferably in Simulation domain.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement.

What You'll Be Doing:

• Designing and implementing verification environments to ensure the correctness of Interface IP protocols.
• Creating and executing detailed test plans to verify complex ASIC designs.
• Developing and maintaining verification IP and testbenches using SystemVerilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications.
• Enhancing the robustness and efficiency of our verification processes and methodologies.
• Contributing to the successful launch of Interface IP products, impacting various industries.
• Driving innovation and excellence within the verification team.
• Improving the overall performance and functionality of Synopsys' IP offerings.
• Fostering a culture of continuous improvement and technical excellence.

What You'll Need:

• Extensive experience in ASIC digital verification, specifically with Interface IP protocols, such as PCIe, CXL, DDR, Ethernet.
• Proficiency in SystemVerilog and UVM methodologies.
• Strong understanding of digital design and verification concepts.
• Experience with simulation tools such as VCS, ModelSim, or similar.
• Excellent problem-solving skills and attention to detail.

Who You Are:

• Detail-oriented with a strong analytical mindset.
• Excellent communicator, able to convey complex technical concepts clearly.
• Collaborative team player who thrives in a dynamic environment.
• Proactive and self-motivated, with a commitment to continuous learning.
• Mentor and leader, capable of guiding and developing junior engineers.

The Team You'll Be A Part Of:

You will be part of a highly skilled and motivated verification team focused on delivering cutting-edge Interface IP solutions. The team is dedicated to maintaining the highest standards of quality and performance, working collaboratively to tackle complex verification challenges. You will have the opportunity to work alongside industry experts and contribute to the development of next-generation technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our mobile app is built using Swift and follows the MVVM-C architecture. We use a range of frameworks and tools, including RxSwift, SnapKit, Realm, and Sourcery. We are looking for someone who is experienced in iOS development and has a strong understanding of software design principles.

As a senior engineer, you will be expected to take ownership of your work and make decisions about the best approach to solving problems. You will also be expected to mentor and guide junior engineers and contribute to the growth and development of our team.

We offer a competitive salary and a range of benefits, including 25 days' holiday, an extra day's holiday for your birthday, and annual leave increased with length of service. We also offer a salary sacrifice scheme, company-enhanced pension scheme, life insurance, and private medical insurance.

If you're passionate about iOS development and want to work for a company that is changing the face of banking, then we'd love to hear from you.

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As an iOS engineer at Starling, you'll be responsible for building and maintaining our iOS application. This will involve working on new features, fixing bugs, and improving the overall performance of the app. You'll also be working closely with our cross-functional feature teams to ensure that our application meets the needs of our customers.

We're looking for someone who is passionate about building high-quality software and has a strong understanding of iOS development. You should be comfortable working in a fast-paced environment and be able to take ownership of your work. We offer a competitive salary and a range of benefits, including 25 days' holiday and an extra day's holiday for your birthday.

If you're interested in joining our team, please submit your application. We look forward to hearing from you!

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Date posted: 03/09/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect.

Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and accomplished digital design engineer with an unyielding drive for excellence.

You thrive in technically challenging environments, where your deep understanding of RTL design and system architecture allows you to craft innovative solutions for complex problems.

With a solid foundation in electrical engineering or VLSI, you have accumulated over five years of hands-on experience in designing and implementing ASIC solutions, particularly focusing on high-performance protocols such as DDR PHY, PCIe, USB, or HBM.

Your expertise extends beyond individual contribution—you are equally comfortable leading and mentoring small design teams, fostering an environment of collaboration and shared learning.

What You’ll Be Doing:

• Lead and Drive all aspects of complete IP Design execution from start to end.

• Architecting, designing, and implementing state-of-the-art RTL for the next-generation high-performance DDR PHY and related IP cores.

• Translating standard and functional specifications into detailed architecture, micro-architecture, and design documentation for medium- to high-complexity features.

• Contributing as an individual designer and also lead other engineers in —handling RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.

• Collaborating with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.

• Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.

• Engaging in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.

• Troubleshooting and resolving design and verification issues, ensuring robust and high-quality deliverables.

The Impact You Will Have:

• Directly contributing to the design and delivery of high-performance IP cores that power industry-leading semiconductor solutions worldwide.

• Elevating Synopsys’ reputation for technical excellence and innovation in the IP design space.

• Accelerating the adoption of advanced protocols and interfaces in cutting-edge technologies.

• Enabling customers to achieve faster time-to-market and superior silicon performance.

• Mentoring and uplifting team members, fostering a culture of knowledge sharing and technical growth.

• Driving continuous improvement in design methodologies, enhancing efficiency and product quality.

• Supporting Synopsys’ mission to remain at the forefront of the Era of Pervasive Intelligence through breakthrough silicon solutions.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.

• 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.

• Past experience of leading IP deign projects, team.

• In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.

• Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.

• Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).

• Familiarity with scripting languages such as Perl or Shell—an advantage.

• Demonstrated ability to technically lead or mentor small teams of engineers.

Who You Are:

• A collaborative team player who thrives in a multi-site, multicultural environment.

• An effective communicator, able to translate complex technical concepts for diverse audiences.

• A proactive problem-solver with strong analytical and troubleshooting skills.

• Self-motivated, showing high initiative and ownership of responsibilities.

• Adaptable and eager to learn, always seeking opportunities for personal and professional growth.

• Committed to fostering a positive, inclusive, and innovative team culture.

The Team You’ll Be A Part Of:

You will join the R&D Solutions Group at our Bengaluru Design Center, a dynamic and diverse team dedicated to the design and development of industry-leading DesignWare IP cores.

As a Technical Individual Contributor, you will collaborate with global experts in a multi-site environment, contributing to technically challenging projects that push the boundaries of silicon design.

The team values innovation, continuous learning, and the sharing of knowledge, offering ample opportunities for growth and leadership.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Benefits

At Synopsys, innovation is driven by our incredible team around the world.

We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day.

We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

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Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

15159

Remote Eligible

No

Date Posted

02/04/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an enthusiastic and detail-oriented SoC RTL Performance Verification Engineer with a passion for developing and deploying verification solutions for System on Chip (SoC) designs. With a strong background in RTL hardware design and verification, you excel in using industry-standard languages like Verilog and SystemVerilog. Your expertise in developing ZeBu emulation-based verification IP (transactor) and solutions makes you a valuable asset to any team. You thrive in dynamic environments, tackling complex problems creatively while adhering to company policies and procedures. Your communication skills are exemplary, allowing you to work effectively with both internal teams and external clients. With a deep understanding of protocols like AMBA AXI/CHI and proficiency in UNIX and scripting, you bring a comprehensive skill set to the table, ready to make an impact in the rapidly evolving field of SoC performance verification.

What You’ll Be Doing:

• Developing SoC Performance Validation (PV) flow and components (transactor model and CI/CD automation) on ZeBu emulator.

• Creating emulation-based transactor and solutions using SystemVerilog and C++.

• Providing technical support and guidance to customers during the deployment of the ZeBu emulator.

The Impact You Will Have:

• Ensuring the reliability and performance of customer SoC designs through rigorous validation processes.

• Enhancing the capabilities of the ZeBu emulator transactor to meet evolving industry standards and customer needs.

• Contributing to the development of innovative SoC PV solutions that set Synopsys apart from competitors.

• Supporting customers in achieving their design and performance goals, thereby strengthening Synopsys' market position.

• Driving continuous improvement in SoC PV methodologies, leading to more efficient and effective processes.

• Fostering collaboration and knowledge sharing within the team, enhancing overall performance and innovation.

What You’ll Need:

• Bachelor's degree in Electrical Engineering or a related field (RTL design/verification) with a minimum of 12+ years of experience.

• A solid understanding of the SoC architecture among HW IPs, AMBA system buses, and LPDDR memory controllers in a mobile AP.

• Proficiency in developing emulation-based transactor models and solutions using SystemVerilog and C++.

• Proficiency with UNIX and scripting.

The Team You’ll Be A Part Of:

You will be part of a dynamic and innovative team focused on developing and deploying cutting-edge verification solutions for SoC designs. The team values collaboration, continuous learning, and a commitment to excellence, working together to drive technological advancements and deliver exceptional results for our customers.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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You are a natural collaborator and mentor, able to bridge the gap between technical and non-technical stakeholders. Your global perspective and excellent communication skills enable you to work seamlessly with cross-functional teams and customers around the world. You are energized by opportunities to lead, whether it’s guiding feature rollouts, solving tough engineering challenges, or supporting cutting-edge customer deployments. Always eager to learn and adapt, you stay at the forefront of industry advances in FPGA, high-speed protocols, and system design. Your commitment to quality, innovation, and continuous improvement sets you apart as a leader in your field.

What You’ll Be Doing:

• Architecting, designing, and implementing PCIe/CXL-based FPGA subsystems for advanced SoC emulation and prototyping platforms.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs, ensuring high performance and efficient resource usage.
• Designing and integrating high-speed serial interfaces, DMA engines, memory/cache-coherent protocols, and complex system interconnects.
• Leading hardware validation and debugging activities across both hardware and software domains to deliver robust, production-quality solutions.
• Collaborating with R&D, Applications, Field Engineering, and Marketing teams to gather requirements, define features, and support global customer deployments.
• Driving alpha/beta feature rollout, providing expert technical support, and ensuring successful adoption of ZeBu/HAPS platforms by customers worldwide.

The Impact You Will Have:

• Enabling industry-leading SoC emulation and prototyping platforms that accelerate time-to-market for Synopsys customers.
• Delivering high-performance, reliable hardware solutions that set benchmarks in PCIe/CXL protocol integration and validation.
• Enhancing the capabilities of ZeBu and HAPS platforms, empowering semiconductor companies to innovate faster and more efficiently.
• Driving adoption of advanced emulation technologies across AI, server, storage, and data center markets.
• Mentoring and guiding engineering teams, fostering a culture of technical excellence and innovation.
• Building lasting partnerships with global customers by providing expert-level support and thought leadership in high-speed protocol design

What You’ll Need:

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of experience in ASIC/FPGA logic design for complex SoC-level systems.
• Expert-level knowledge of PCIe (Gen4–Gen6) and/or CXL (1.1/2.0/3.0) protocols, including link training, TLP/CXL.io/cache/mem, flow control, and error handling.
• 7+ years of hands-on Xilinx FPGA experience, including transceiver/SERDES integration and FPGA prototyping flows.
• Strong proficiency in RTL development (SystemVerilog/Verilog) and comprehensive understanding of the hardware development cycle (simulation, synthesis, timing analysis).
• Solid grasp of FPGA architecture, clocking/reset design, CDC, and debugging high-speed interfaces.
• Experience in Unix/Linux development environments.

Who You Are:

• Collaborative team player with excellent communication skills and a global mindset.
• Proactive problem solver who thrives in dynamic, fast-paced environments.
• Strong technical leader and mentor, passionate about sharing knowledge and guiding teams.
• Detail-oriented, self-motivated, and committed to delivering high-quality, reliable solutions.
• Adaptable and eager to stay updated with the latest industry trends and technologies.
• Customer-focused, with a dedication to supporting and enabling client success.

The Team You’ll Be A Part Of:

You will join a world-class, multidisciplinary engineering team passionate about developing state-of-the-art emulation and prototyping solutions. The team values technical excellence, innovation, and collaboration, working closely with global colleagues in R&D, customer support, and product management. Together, you will tackle some of the most complex challenges in hardware design, driving the future of high-speed, scalable SoC platforms for leading-edge industries.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Responsibilities:

• Single point of contact in the core functional area for all product safety and compliance topics.
• Translate system-level regulatory requirements to component-level engineering requirements to ensure robust compliance.
• Maintain awareness of technology and regulatory development to help Ford's vehicles robustly comply globally.
• Ensure Safety and Compliance requirements are cascaded at the right time, understood by the right stakeholders, and include system and component implications.
• Represent safety and compliance for the core functional area in all Design Reviews and key decision forums, including review of all deviation requests and change requests.
• Ensure alignment of key safety and compliance controls of components, sub-systems, and systems throughout the Failure Mode Avoidance process, facilitating cross-functional collaboration between hardware, software, and features engineering teams as well as downstream manufacturing and supplier processes.
• Partner with Campaign Prevent Specialists and Program Compliance Attribute Leads in Fresh Eyes Reviews and issue resolution.
• Assess Stop Ships and field or build issues for potential cross-vehicle line effects, ensure process improvements and Prevent Action Closure remedies are properly communicated and implemented into Failure Mode Avoidance documents, deliverables, and processes beyond same-part assessment to include related families or functional considerations.
• Deliver on-going training to core functional area, technical specialists, and Hardware/Software/Features Engineering teams to promote a strong safety/compliance culture throughout the enterprise.
• Review processes, connected data, warranty, prototype issues, Compliance Demonstration Report timing, and functional performance to recommend changes to audits and checks of Design, Release, and Manufacturing attributes.

Qualifications:

• Bachelor's Degree in Engineering
• Experience in Product Development (PD) and/or Vehicle Homologation & Compliance (VH&C)
• Experience in powertrain, fuel systems, or thermal systems as a D&R engineer
• FEDE experience with requirements: classification, assessment, and evidence
• Strong basis of understanding Ford's processes (technology development, product development (GPDS), design validation and verification, vehicle operations, and potential defect investigations)
• Positive problem-solving attitude and conflict resolution skills
• Experience with 3L5W, G8D, and PAC papers
• Familiarity with DFMEA's and severity ratings, including the new rating tables
• Knowledge of FMVSS requirements and ability to apply them throughout the engineering process
• Ability to collaborate and connect cross-functionally to implement transformative process improvements
• Strong communication and cross-functional networking skills
• Strong decision-making skills and resolve to raise issues to the right people at the right time
• Global understanding of Ford's processes and products for technical read-across
• Ability to critically evaluate data to make key decisions
• Strong desire to improve safety and drive safety culture throughout Ford
• Desire to get hands-on during Fresh Eyes Reviews (FER's)

You may not check every box, or your experience may look a little different from what we've outlined, but if you think you can bring value to Ford Motor Company, we encourage you to apply!

As an established global company, we offer the benefit of choice. You can choose what your Ford future will look like: will your story span the globe, or keep you close to home? Will your career be a deep dive into what you love, or a series of new teams and new skills? Will you be a leader, a changemaker, a technical expert, a culture builder…or all of the above? No matter what you choose, we offer a work life that works for you, including:

• Immediate medical, dental, vision, and prescription drug coverage
• Flexible family care days, paid parental leave, new parent ramp-up programs, subsidized back-up child care, and more
• Family building benefits including adoption and surrogacy expense reimbursement, fertility treatments, and more
• Vehicle discount program for employees and family members and management leases
• Tuition assistance
• Established and active employee resource groups
• Paid time off for individual and team community service
• A generous schedule of paid holidays, including the week between Christmas and New Year's Day
• Paid time off and the option to purchase additional vacation time.

For more information on salary and benefits, click here: https://fordcareers.co/GSRSP1

This position is a range of salary grades SG5-SG8.

Visa sponsorship is not available for this position.

Candidates for positions with Ford Motor Company must be legally authorized to work in the United States. Verification of employment eligibility will be required at the time of hire.

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At Ford Credit, we take immense pride in being a subsidiary of Ford Motor Company, a global leader renowned for its strong sense of family and a firm commitment to making the world a better place. We create a culture of diversity, equity, and inclusion as we believe it is fundamental to achieving our business objectives and essential to treating every employee with the utmost dignity and respect.

For over 65 years, we have been instrumental in placing people in the driver's seat of exceptional Ford and Lincoln vehicles, contributing to the triumph of our 120-year-old Ford Motor Company. We've offered financing, tailored services, and professional expertise to 5,000 dealerships and more than 4 million customers across 100 countries.

As we envision the future of mobility, we present a broad spectrum of opportunities for you to enhance your career trajectory while shaping the transport of tomorrow. Joining us means embracing the liberty to pursue and define your aspirations, anchored in our conviction that the freedom to move is a catalyst for human advancement.

Responsibilities

• Collaborate with product managers, designers, and other stakeholders to understand the product vision, and requirements.

• Provide technical insights, feasibility assessments, translate the requirements into technical specifications considering factors like performance, scalability, and maintainability.

• Designing system architecture and implementing scalable APIs and Microservices

• Demonstrates exceptional technical ability in actually writing software, hands-on keyboard, through proof of concepts and spikes with teams.

• Partner across functions, building relationships that allow you to influence the strategy, plans and work to improve customer value through service, experience, availability, quality, and cost.

• Be an active participant in reviewing, evaluating, and providing feedback on product designs and architectures with an engineering focus.

• Guide and influence design decisions ensuring the product can be built effectively. Review and approve technical designs, architecture diagrams, and code to ensure alignment with specifications and best practices.

• Create prototypes, proof of concepts, or minimum viable products to validate technical concepts and gather feedback. Facilitate communication between teams, addressing technical concerns and ensuring a shared understanding of requirements.

• Develop and socialize new engineering principles and practices fit for purpose for the organization.

• Evaluating and recommending new and emerging products and technologies.

• Partnering with the engineering teams, design, research and end-users to deliver updates.

• Facilitate in highly collaborative Full Stack eXtreme Programming (XP) practices including but not limited to Pair Programming, Test Driven Development (TDD), DevOps, Continuous Integration and Continuous Deployment (CI/CD), Security (SAST/DAST), Monitoring/logging/tracing/ tools (SPLUNK, Dynatrace, etc…), and Agile practices including but not limited to Stand-ups, backlog grooming, sprint demos and journey mapping.

• Dependency and stakeholder management

• Documentation: Create and maintain technical documentation, including specifications, architecture diagrams, and user manuals.

• Continuous Improvement: Stay updated on industry trends, emerging technologies, and best practices related to product development and engineering. Identify opportunities for process improvements, automation, and optimization within the product development lifecycle.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, Information Technology or related field.

• 7+ years of advanced professional experience on Software design/development and execution.

• 7+ years of work experience in Java 8 or above

• 5+ years of work experience in Spring Platform (Spring MVC, Spring Boot, Spring JDBC, Spring Cloud)

• 3+ years of work experience in Microservice architecture and SOAP or REST APIs

• 3+ years of Cloud Native Development experience on GCP Platform CloudRun, Cloud Functions, Containers via Podman.

• Messaging/Streaming - GCP Pub/Sub, Kafka, GCP EventArc.

• Persistence - Buckets, PostgreSQL Bigtable

• Experience in Agile project involvement, Software Craftsmanship

• Experience in Front end client development frameworks (React/Angular)

• Experience in Code quality tools (42Crunch, SonarQube, CheckMarx, etc…)

• CI/CD – Tekton or relative exposures on GIT hub, Jenkins, Maven, Gradle, etc

• Exposure and knowledge to Asset Finance tools.

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We are looking for a hardware verification engineer who will perform verification of complex leading-edge security systems IP components. Be a part of a world-class team, building advanced security solutions that meet the Synopsys high quality standard for best-in-class products. These products are found in some of the most advanced, high-tech devices today in areas like automotive, networking, mobile, and IoT applications.

Responsibilities

• Performing design verification of cutting-edge IP components and subsystems used in high-profile security applications.
• Developing comprehensive product verification strategies, including test specifications, detailed test plans, and thorough test reports.
• Implementing, developing, and automating test environments for regression testing to ensure robust product quality.
• Collaborating closely with design engineers and architects to debug products and resolve defects efficiently.
• Staying current with the latest verification methodologies and tools, integrating state-of-the-art practices into your workflow.
• Hardware verification of IP cores and subsystems with techniques such as SystemVerilog /UVM and Formal Verification
• Proactively researching and integrating new developments in the domain of embedded security

Requirements

• Proven expertise in verification of digital hardware IP components
• Deep technical knowledge of and experience with modern verification methodologies including UVM, assertion-based verification, coverage driven methodology and formal verification
• Good knowledge about IC Design flows and excellent problem solving and debugging skills
• Experience with verification flow automation and scripting.
• Strong communication (written and verbal) and interpersonal skills
• Bachelor’s or Master’s degree in Electrical Engineering or Computer Science, with 8+ years of relevant experience.
• Familiarity with security and cryptographic protocols is desirable.

What You’ll Be A Part Of

You’ll join the Security IP group in Ottawa, world-class, security-focused team of hardware and software engineers dedicated to advancing the best in security technologies. The team works collaboratively to design, verify, and deliver leading-edge security solutions found in the world’s most advanced devices, from automotive to IoT. Together, you’ll challenge the status quo and set new benchmarks in embedded systems security.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Design Verification Engineer

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry-standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

XML job scraping automation by YubHub

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

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RTL & Codesign Engineer

Location

San Francisco

Employment Type

Full time

Department

Scaling

Compensation

• $225K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

In this role you will:

• Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems

• Contribute to architectural studies including performance modeling and feasibility analysis.

• Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.

• Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.

• Build and review performance and functional models to validate design intent.

• Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.

You Might Thrive In This Role If You Have:

• Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.

• Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.

• Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.

• Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.

• Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.

• Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.

• Passion for building industry-leading massive-scale hardware systems.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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About the Team

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems.

In this role you will:

• Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.

• Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.

• Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.

• Work closely with designers and verification engineers to turn real pain points into durable tools.

• Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.

• Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts.

• Help enable PPA optimization loops by building analysis and automation around area, timing, and power tradeoffs, and by improving tooling that impacts those outcomes.

You might thrive in this role if:

• Demonstrated ability to build and maintain software (projects, internships, research, open source, or equivalent experience).

• Strong CS fundamentals: data structures, algorithms, debugging, and software design.

• Proficiency in at least one of Rust, C++, or Python (and willingness to learn the rest).

• Familiarity with digital design concepts and the ability to read RTL (Verilog/SystemVerilog) or equivalent hardware descriptions.

• Familiarity with compiler or IR-based ideas (representations, passes, transformations, lowering), through coursework or projects.

• Comfort operating in ambiguity and iterating quickly with users of your tools.

Nice to have skills:

• Exposure to compiler and hardware toolchains such as XLS/DSLX, LLVM, Chisel/FIRRTL, CIRCT/MLIR, other novel hardware languages (e.g. HardCaml, SpinalHDL, Spade, PyMTL, Clash, BlueSpec, PyRope)

• Experience with Verilog tooling ecosystems (Yosys/RTLIL, Verilator, Slang) or writing tooling around them.

• Experience with build and test infrastructure (Bazel, CI systems, fuzzing, performance testing).

• Prior work touching synthesis, place and route, static timing analysis, or other PPA-related workflows.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world.

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What you'll do

• Leading end-to-end deployment and integration of Verification IP at strategic customer accounts, ensuring seamless adoption and success.
• Defining and implementing robust verification strategies for Arm-based SoCs, with a focus on interconnect and coherency protocol validation.

What you need

• Deep expertise in UVM, SystemVerilog, and advanced protocol verification methodologies.
• Hands-on experience with Verification IPs (VIPs) and Transactors in both simulation and emulation environments.

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What you'll do

• Designing and implementing RTL-based HBM controller IP cores for cutting-edge SoC applications.
• Interpreting and translating standard and product functional specifications into detailed micro-architectures.

What you need

• Extensive hands-on experience with RTL design and micro-architecture development from functional specifications.
• Proficiency in verification methodologies (UVM/VMM/OVM), SystemVerilog, and object-oriented verification techniques.

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What you'll do

• Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.
• Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.
• Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.
• Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.
• 4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
• Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
• Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

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What you'll do

As a HBM Design Verification Engineer, Principal, you will be responsible for developing verification strategies and plans for ASIC/SoC projects, defining and implementing testbench architecture and methodologies, building testbench infrastructure and verification components, and creating verification item lists, coverage models, and checkers.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) with 10–15+ years of relevant experience

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What you'll do

• Developing and executing comprehensive verification plans for complex ASIC designs, focusing on next-generation HBM (High Bandwidth Memory) products.
• Writing and maintaining advanced testcases using SystemVerilog and UVM methodologies to ensure thorough coverage and robust verification.
• Debugging and analyzing complex testbench and design-related issues, collaborating closely with design and mixed-signal engineering teams.

What you need

• Bachelor’s or Master’s degree in Electrical Engineering (BSEE or MSEE) with a minimum of 10 years of digital design/verification experience.
• Proven experience in writing and maintaining testcases using SystemVerilog/UVM.
• Strong debugging skills for complex testbench and design-related issues.
• Solid understanding of digital circuit design concepts and principles.
• Proficiency with scripting languages such as Python or Perl for automation and workflow enhancement.

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What you'll do

• Developing and maintaining SerDes system models for NRZ and PAM4 transceivers targeting PCIe (128Gbps+) and Ethernet (200Gbps+) standards.
• Running comprehensive system simulations to verify and sign-off design performance across multiple protocols and channels.

What you need

• M.Sc. or Ph.D. in Electrical or Computer Engineering.
• Strong experience modeling circuits and systems in MATLAB/Simulink.
• Expertise in designing high-speed analog CMOS circuits.
• Solid understanding of DSP and communications theory, including equalization, coding, and noise/crosstalk filtering.
• Proficiency in analyzing link budgets for NRZ and/or PAM4 high-speed serial links.
• Familiarity with wireline protocols (PCIe, Ethernet, JESD204C, CPRI) and optical protocols (LINEAR, RTLR).
• Experience with circuit topologies used in high-speed SerDes Tx/Rx and Tx/Rx equalization techniques.
• Hands-on lab testing for high-speed serial links and proficiency in C/Verilog-A/systemVerilog.

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What you'll do

• Partnering with design teams to define verification requirements
• Developing test plans from specifications
• Building and maintaining UVM testbenches and agents

What you need

• B.Sc./M.Sc. in a relevant engineering field
• 10+ years in ASIC/UVM verification

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What you'll do

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in SystemVerilog and Verilog for RTL development.

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What you'll do

• Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.

What you need

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

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What you'll do

• Leading and managing a team of ASIC Digital Verification engineers, providing guidance and mentorship;
• Creating and maintaining testbenches using SystemVerilog and UVM methodologies;

What you need

• Extensive experience in ASIC digital verification, particularly with HBM (or DDR/LPDDR) protocols;
• Proficiency in SystemVerilog, UVM, and other verification tools and methodologies;

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What you'll do

• Implementing reference and unified verification flows for Synopsys digital IP products using leading EDA tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.
• Building robust, scalable verification infrastructures from the ground up to support diverse and complex IP and SoC projects.

What you need

• Minimum 5 to 10 years of hands-on experience in IP/SoC verification, with a proven track record of technical leadership.
• Strong expertise in using Synopsys verification tools such as VCS, Verdi, VMS Execution Manager, Verdi Planner (HVP), and VIPs.

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What you'll do

• Administer, configure, and optimize the Commvault platform.
• Design and implement scalable backup and recovery solutions.

What you need

• At least 5 years hands-on experience with Commvault Complete Backup & Recovery in enterprise environments.
• Strong expertise in Storage Policies, Subclients, Schedules, Performance Tuning, Deduplication Database (DDB) maintenance and troubleshooting, VMware VADP backups, Hyper-V, and virtualized environments, Cloud storage (Azure, AWS, or GCP), Enterprise storage systems (NetApp, Dell EMC, HPE, etc.).

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What you'll do

• As part of the product team, you will be a key contributor, developing the solution for high-volume, high transaction applications specifically targeted to support the game development teams across the entire global enterprise.
• You will take part in any negotiations or discussions regarding the necessary requirements and provide feedback to all parties involved.
• You will participate in code reviews and provide constructive feedback on design and implementation to peers.
• Report progress and status through regular email or face-to-face communication with appropriate leads/managers.

What you need

• 5+ years of experience developing enterprise level software solutions.
• 5+ years of broad experience working with development technologies including Microsoft .NET (C#), ASP.NET/MVC, WCF/Web API/REST, JavaScript frameworks, HTML+CSS3+Javascript.
• 5+ years of experience in database development using Microsoft SQL Server or similar RDBMs and related programming data access technologies (ADO.NET, ORMs, OData)
• 5+ years of experience applying design patterns, methodologies and recognized practices like unit testing, dependency injection, test-driven development, continuous integration, and delivery.
• 3+ years of experience developing cloud-based applications using PaaS (Platform as a Service) and IaaS (Infrastructure as a Service) offerings from leading vendors such Amazon’s AWS and Microsoft Azure

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What you'll do

Collaborating closely with analog, digital, and hardware teams to ensure holistic design and verification coverage.

• Developing and maintaining comprehensive simulation and verification plans for IP, aligning with reliability and performance targets.

What you need

• MSc or PhD in Electrical/Computer Engineering, with 10+ years of relevant industry experience.

Why this matters

Advance high-speed connectivity for enterprise and hyperscale applications worldwide.

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What you'll do

You will be responsible for developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.

• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.

Why this matters

Drive the development of cutting-edge HBM PHY IP, enabling industry-leading memory bandwidth for next-generation computing systems.

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What you'll do

You will join the Synopsys IP Group, a highly collaborative and innovative team focused on developing leading-edge interface IP solutions for memory technologies.

• Developing detailed verification testplans and comprehensive functional coverage models for complex memory interface IP.
• Implementing scalable UVM testbench infrastructure and designing robust test cases to verify training firmware functionality on RTL PHY models.

What you need

• Proficiency in SystemVerilog and UVM, with hands-on experience using simulation and waveform debugging tools.
• Strong background in developing verification solutions focused on productivity, performance, and throughput.

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What you'll do

• Take an active part in developing high-quality tools that support game development and content creation workflows.
• Implement maintainable applications using C# and WPF within a large, long-lived codebase.

What you need

• Professional experience with C# and C++ (2+ years).
• Strong professional experience developing applications (WPF) and User Interface Design.

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What you'll do

Develop reusable verification environments and testbenches using UVM.

• Plan, maintain, and execute verification strategies for ASIC/SoC projects.

• Create test cases, set up and run regressions, and close coverage.

What you need

Minimum 6 years' SoC/ASIC verification experience.

• Strong SystemVerilog (UVM preferred) skills.

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What you'll do

• Develop and maintain high-quality digital verification environments, including UVM, SystemVerilog, and C++.
• Collaborate with cross-functional teams to develop and verify complex digital designs.
• Identify and prioritize verification tasks to meet project timelines and quality standards.
• Develop and execute verification plans, including testbenches, test cases, and coverage metrics.
• Collaborate with design teams to develop and verify complex digital designs.

What you need

• Bachelor's degree in Computer Science, Electrical Engineering, or related field.
• 10+ years of experience in digital verification, including UVM, SystemVerilog, and C++.
• Strong understanding of digital design principles and verification methodologies.
• Excellent communication and collaboration skills.
• Experience with Agile development methodologies and version control systems.

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You'll support the ADAS team in developing driver assistance systems for passenger cars and commercial vehicles.

• Coordinate test vehicles and integrate measurement equipment
• Commission measurement technology and sensorics of the vehicle
• Conduct measurements according to a test catalog
• Evaluate, analyze, and document the results
• Collaborate directly with the project team
• Perform technical documentation
• Create presentations

What you need

• Studium im Bereich Maschinenbau, Elektrotechnik, Fahrzeugtechnik, Mechatronik oder artverwandter Disziplinen
• Systemverständnis
• Grundlagen im Bereich ADAS Funktionen und Sensorik
• Analytisches, systematisches und zielorientiertes Arbeiten mit hoher Eigenständigkeit
• Begeisterung und Interesse, ein Zukunftsthema der Automobilindustrie mitzugestalten und weiterzuentwickeln
• Sicher im Umgang mit den gängigen MS Office-Anwendungen, insbesondere Word, Excel und PowerPoint
• Gute Deutsch- und Englischkenntnisse
• Hohes Maß an Selbstständigkeit, Teamfähigkeit, Verantwortungs- und Qualitätsbewusstsein

Why this matters

This role is about supporting the development of driver assistance systems for passenger cars and commercial vehicles. You'll work with a team to design and test these systems, and contribute to the creation of innovative solutions for the automotive industry.

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