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You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills and problem-solving mindset enable you to convey complex ideas to various stakeholders, deliver robust solutions and mentor others, making you a key contributor to innovative projects.</p>\n<p>As a Sr Staff Engineer, you will lead the physical implementation of high-speed interface IPs from RTL to GDS, ensuring timing and physical sign-off. You will collaborate with cross-functional teams to integrate and verify IP designs to achieve project goals. You will also provide technical guidance and mentorship, continuously improving design methodologies and processes to enhance efficiency and quality.</p>\n<p>The impact you will have is driving the development of high-performance physical IP that powers next-generation technologies, ensuring the reliability and efficiency of physical design solutions in our products, contributing to the success of Synopsys&#39; strategic goals through innovative design solutions, sharing technical expertise to elevate team capabilities, fostering a culture of continuous improvement and excellence within the engineering team, and supporting the adoption and usability of our products by providing top-tier engineering expertise.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_89a82cda-38e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-staff-engineer-in-hcmc-or-da-nang/44408/94030515824","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Design","Mixed Signal IPs","Test Chips","RTL to GDSII","Synopsys Tools and Methodologies"],"x-skills-preferred":["Chip Architecture","Circuit Design","Verification","Problem-Solving","Communication"],"datePosted":"2026-04-24T14:11:10.554Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Design, Mixed Signal IPs, Test Chips, RTL to GDSII, Synopsys Tools and Methodologies, Chip Architecture, Circuit Design, Verification, Problem-Solving, Communication"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3bb7e3ce-9f9"},"title":"ASIC Physical Design, Principal Engineer","description":"<p>We are seeking a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. 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