Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are: You are a passionate and resourceful ASIC Physical Design engineer ready to tackle the complex challenges of next-generation silicon. With a strong foundation in VLSI concepts, you thrive in dynamic, collaborative environments and are motivated by the opportunity to learn and grow. You are adept at communicating technical ideas, whether collaborating with teammates in Bangalore or interacting with colleagues in the US. Your attention to detail and commitment to quality ensure your designs meet stringent performance and power requirements. You bring a proactive attitude, always seeking new ways to optimize and innovate, and you embrace challenges such as achieving timing closure at GHz frequencies and integrating mixed-signal macros. Your experience with DDR IP or high-speed interface implementations is a strong asset, and you are eager to contribute to world-class products at the forefront of semiconductor technology. You value teamwork, knowledge sharing, and continuous improvement, recognizing that the best solutions are built together. If you are looking to make an impact at the leading edge of physical design, Synopsys is the place for you.
\nWhat You'll Be Doing: Implement and integrate state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below). Drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability. Collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges. Integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions. Design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution. Participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies. Support the implementation of best practices in floorplanning, placement, routing, and power optimization. Mentor junior engineers and contribute to team knowledge sharing initiatives.
\nThe Impact You Will Have: Enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products. Advance Synopsys' leadership in IP implementation at cutting-edge technology nodes. Champion best-in-class timing closure and integration practices, raising the bar for design excellence. Facilitate seamless cross-site collaboration, ensuring global project success. Drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings. Accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.
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