Saronic Technologies is seeking a Senior Electrical Engineer with deep experience in electro-optical (EO) and infrared (IR) camera systems to join our Electrical Engineering - Advanced Development group.
\nThis position focuses on research, evaluation, and integration of imaging and sensing systems - including visible, thermal, and multispectral cameras - that support autonomous vessel perception, situational awareness, and target tracking.
\nThe ideal candidate will lead efforts in system benchmarking, performance analysis, and trade study development for EO/IR technologies across multiple market offerings. This role combines hands-on testing, technical analysis, and system-level design to shape Saronic’s next generation of perception capabilities.
\nKey Responsibilities
\nRequired Qualifications
\nPreferred Qualifications
\nBenefits
\nPhysical Requirements
\nAdditional Information
\nThis role requires access to export-controlled information or items that require “U.S. Person” status. As defined by U.S. law, individuals who are any one of the following are considered to be a “U.S. Person”: (1) U.S. citizens, (2) legal permanent residents (a.k.a. green card holders), and (3) certain protected classes of asylees and refugees, as defined in 8 U.S.C. 1324b(a)(3).
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\nAs a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.
\nKey responsibilities include:
\nAs a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nWe are seeking a Staff Engineer (Virtual Prototyping) to join our team in Moreira, Porto, Portugal. As a Staff Engineer, you will be responsible for developing and delivering high-performance simulation models for automotive, enterprise, telecommunications, and cloud platforms. You will also configure and bring up complex software stacks and drivers on simulated hardware platforms, collaborate with other development teams, IP owners, third-party suppliers, support engineers, and customers to identify, implement, and deliver solutions.
\nKey Responsibilities:
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\nRequirements:
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\nYou are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.
\nWhat You’ll Be Doing:\nSpecify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.\nDevelop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.\nDesign, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.\nPerform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.\nCollaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.\nLeverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.\nContribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.
\nThe Impact You Will Have:\nEnsure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets.\nDrive innovation in verification methodologies, setting new standards for efficiency and coverage.\nEnhance time-to-market by identifying and resolving design and verification issues early in the development cycle.\nStrengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus.\nMentor and support junior engineers, fostering a culture of learning and continuous improvement.\nContribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.
\nWhat You’ll Need:\nBSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.\nExpertise in developing HVL (System Verilog)-based verification environments and testbenches.\nStrong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.\nProficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.\nSolid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.\nFamiliarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.\nDemonstrated ability to work with functional coverage-driven methodologies and quality metric goals.
\nWho You Are:\nAnalytical thinker with strong problem-solving and debugging skills.\nExcellent verbal and written communication abilities.\nTeam player who thrives in collaborative, multi-site environments.\nProactive, self-motivated, and able to take initiative on challenging projects.\nDetail-oriented, quality-focused, and driven by a desire to excel.\nAdaptable and eager to continuously learn and apply new technologies.
\nThe Team You’ll Be A Part Of:\nYou will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.
\nRewards and Benefits:\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nAt Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.
\nA peek inside our office
\nBenefits:\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nVisit Benefits Page
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\nASIC/SoC Presales Applications Engineer - 16648
\nSunnyvale, California, United States
\nSave
\nCategory: EngineeringHire Type: Employee
\nJob ID 16648Base Salary Range $184000-$276000Date posted 03/31/2026
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.
\nYou Are:
\nYou are a seasoned ASIC, SoC, or Chiplet Architect, Manager, or Design Engineer, bringing extensive expertise in IC Digital, Mixed Signal, or Analog Design. Your technical prowess is matched by your ability to engage and inspire customers, translating complex engineering concepts into clear, impactful solutions. You thrive in fast-paced, dynamic environments and are adept at navigating competitive landscapes. Your organizational skills and self-motivation ensure you deliver on ambitious goals, while your creative approach to problem-solving enables you to overcome challenges with finesse. You build trust and rapport quickly, fostering long-lasting relationships with both internal teams and external stakeholders. With a Bachelor’s (15+ years) or Master’s (11+ years) degree in a relevant field, you understand industry protocols such as SerDes, UCIe, PCIe, DDR, USB, MIPI, or Ethernet, bringing added value to each engagement. You are passionate about driving technology forward and contributing to customer success, ready to make a significant impact at Synopsys.
\nWhat You’ll Be Doing:
\nThe Impact You Will Have:
\nWhat You’ll Need:
\nWho You Are:
\nA creative problem solver and strategic thinker, you excel at collaborating with diverse teams and stakeholders. You are driven by a passion for technology, innovation, and customer success, bringing a positive, solutions-oriented mindset to every challenge. Your adaptability and leadership enable you to thrive in high-pressure situations, while your integrity and commitment build trust across all levels of the organization.
\nThe Team You’ll Be A Part Of:
\nYou’ll join a collaborative group dedicated to delivering groundbreaking chip design solutions using Synopsys IP. The team works closely with Sales, R&D, and Marketing, fostering a supportive and innovative environment where your ideas and expertise will help shape next-generation semiconductor products.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nOur Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nJob Description
\nWe Are:
\nAt Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nYou Are:
\nYou are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.
\nResponsibilities
\nArchitecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.
\nTranslating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.
\nLeading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.
\nCollaborating with global teams and engaging directly with customers to understand and refine specification requirements.
\nDriving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.
\nMentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.
\nUtilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.
\nRequirements
\nBachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.
\n4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.
\nDeep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.
\nProficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.
\nFamiliarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.
\nExperience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.
\nKnowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).
\nExposure to quality processes in IP design and verification is an advantage.
\nPrior experience as a technical lead or mentor is highly desirable.
\nWho We Are Looking For
\nInnovative thinker with a solutions-oriented mindset and a passion for technology.
\nExcellent communicator who thrives in collaborative, multicultural, and multi-site environments.
\nNatural leader with mentoring abilities, fostering inclusion and diversity within the team.
\nDetail-oriented professional with strong analytical and problem-solving skills.
\nSelf-motivated, adaptable, and eager to drive technical excellence and process improvements.
\nCommitted to continuous learning and staying ahead of industry trends.
\nThe Team You’ll Be A Part Of
\nYou will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
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\nYou are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.
\nYour technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.
\nYou will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.
\nYou will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.
\nYou will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.
\nYou will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nYou will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
\nYou will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.
\nYou will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.
\nYou will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nPerforming verification tasks for IP cores, including test planning and environment coding at both unit and system levels.
\nDeveloping and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.
\nManaging regression and ensuring adherence to verification methodologies.
\nCollaborating closely with RTL designers and a global team of verification engineers.
\nWorking on next-generation connectivity protocols for commercial, enterprise, and automotive applications.
\nWhat you need
\nBSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.
\nExperience in architecting verification environments for complex serial protocols.
\nProficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.
\nExpertise in verification methodologies such as VMM, OVM, and UVM.
\nKnowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.
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