{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/mentoring-and-talent-development"},"x-facet":{"type":"skill","slug":"mentoring-and-talent-development","display":"Mentoring And Talent Development","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5dc3ce00-3cc"},"title":"Principal Physical Design Engineer – SerDes","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>We are seeking a Principal Physical Design Engineer to lead the physical implementation of high-speed interface IPs and test-chips, taking designs from RTL to GDSII. The ideal candidate will have intimate knowledge of the full design cycle from RTL to GDSII, including chip-level implementation, and experience with advanced FinFET nodes (TSMC 16nm or below) and low-power design techniques.</p>\n<p>The successful candidate will be responsible for driving timing and physical sign-off processes to ensure optimal performance and reliability, collaborating with front-end, analog, CAD, and product teams to solve complex mixed-signal integration challenges, and guiding a team of engineers through project execution, mentoring and developing talent within the group.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading the physical implementation of high-speed interface IPs and test-chips, taking designs from RTL to GDSII</li>\n<li>Driving timing and physical sign-off processes to ensure optimal performance and reliability</li>\n<li>Collaborating with front-end, analog, CAD, and product teams to solve complex mixed-signal integration challenges</li>\n<li>Guiding a team of engineers through project execution, mentoring and developing talent within the group</li>\n</ul>\n<p>The ideal candidate will have 12+ years of digital or physical design experience with recent project tape-outs as a technical driver or project lead, intimate knowledge of the full design cycle from RTL to GDSII, including chip-level implementation, and experience with advanced FinFET nodes (TSMC 16nm or below) and low-power design techniques.</p>\n<p>In addition to technical expertise, the successful candidate will be a collaborative and communicative leader, able to work effectively across diverse teams, autonomous and decisive, comfortable managing multiple priorities and interruptions, and methodology-driven, with a passion for continuous improvement and innovation.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5dc3ce00-3cc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/principal-physical-design-engineer-serdes-16976/44408/94087525936","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["digital design","physical design","high-speed interface IPs","test-chips","RTL to GDSII","advanced FinFET nodes","low-power design techniques","timing and physical sign-off processes","mixed-signal integration challenges","project execution","team leadership","mentoring and talent development"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:17:54.642Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"digital design, physical design, high-speed interface IPs, test-chips, RTL to GDSII, advanced FinFET nodes, low-power design techniques, timing and physical sign-off processes, mixed-signal integration challenges, project execution, team leadership, mentoring and talent development"}]}