{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/mac-sec-engines"},"x-facet":{"type":"skill","slug":"mac-sec-engines","display":"Mac Sec Engines","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9b235f6e-c09"},"title":"IP Design Technical Lead/ Staff ASIC RTL Design Engineer","description":"<p>We are seeking a passionate and forward-thinking digital design expert to join our team as an IP Design Technical Lead/ Staff ASIC RTL Design Engineer. As a key member of our team, you will be responsible for architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.</li>\n<li>Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.</li>\n<li>Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.</li>\n<li>Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.</li>\n<li>4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.</li>\n<li>Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.</li>\n<li>Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9b235f6e-c09","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/ip-design-technical-lead-staff-asic-rtl-design-engineer/44408/90581151808","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","Verilog/SystemVerilog","simulation tools","design flows"],"x-skills-preferred":["data path and control path design","Reed Solomon FEC","BCH codes","CRC architectures","MAC SEC engines"],"datePosted":"2026-03-06T07:24:37.286Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, Verilog/SystemVerilog, simulation tools, design flows, data path and control path design, Reed Solomon FEC, BCH codes, CRC architectures, MAC SEC engines"}]}