We are seeking an experienced Applications Engineer to join our team in Hyderabad. As an Applications Engineer, you will be responsible for developing and validating DRC, LVS, and Fill runsets for the Synopsys IC Validator tool. You will collaborate closely with leading foundries to understand process requirements and deliver high-quality PV runsets for advanced nodes. Your responsibilities will also include automating qualification processes for IC Validator runsets using scripting languages such as Perl, Tcl, and Python. You will troubleshoot and resolve complex layout verification issues, including LVS discrepancies, DRC violations, and DFM challenges. Additionally, you will interface directly with customers and Field Application Engineers (FAEs) to gather requirements, provide technical support, and ensure successful deployment of PV solutions. You will also mentor junior team members, share best practices, and contribute to a knowledge-sharing culture within the team.
\nYou will join a dynamic and diverse team of physical verification experts, tool developers, and field support engineers dedicated to enabling the next generation of semiconductor design. The team thrives on technical collaboration, innovation, and a shared commitment to delivering best-in-class PV solutions to customers worldwide. You will work closely with foundry partners, internal R&D, and field teams, ensuring that Synopsys remains a leader in EDA technology and customer satisfaction.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_52170496-422","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/applications-engineer-icv-runset-development/44408/92715864304","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Physical Verification (PV)","EDA tools such as IC Validator, Calibre, Pegasus, and PVS","Scripting languages such as Perl, Tcl, and Python","CMOS layout, ASIC design flows, and foundry process requirements","DRC, LVS, ERC, and DFM rule decks"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:20.854Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Physical Verification (PV), EDA tools such as IC Validator, Calibre, Pegasus, and PVS, Scripting languages such as Perl, Tcl, and Python, CMOS layout, ASIC design flows, and foundry process requirements, DRC, LVS, ERC, and DFM rule decks"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f3b2a87c-f0c"},"title":"Sr Staff SoC Engineer(Backend)","description":"We are seeking a highly skilled Sr Staff SoC Engineer(Backend) to join our team in Beijing. As a key member of our engineering team, you will be responsible for assisting our customers successfully tape out from Netlist to GDS by using Synopsys EDA tools.
\nYour focus will be in the areas of design planning, floorplanning, place and route, parasitic extraction, signal integrity analysis and prevention, IR drop/EM analysis and physical verification (DRC/LVS).
\nA secondary focus will be in static timing analysis, Low Power Static check and formal verification. You will work as a member of the customer's IC design team, leveraging their experience and Synopsys' best practices to have immediate impact on their current project while transferring valuable knowledge for future projects.
\nYou will interact regularly with customers to identify and eliminate barriers to project success. You will plan and manage delivery of own project-related tasks. You will leverage entire Synopsys team to ensure project success. You will provide feedback to R&D/AE on suggested tool enhancements or issues.
\nYou will work with or as Project Leader to develop technical proposals, working through project life cycle and produce consistently high-quality technical solutions.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_f3b2a87c-f0c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/beijing/sr-staff-soc-engineer-backend/44408/92669904928","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["Floorplan","Place and route","DRC/LVS","IR drop","EM","Signal Integrity","STA","Formal Verification","Synthesis"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:59.298Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Beijing"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"Floorplan, Place and route, DRC/LVS, IR drop, EM, Signal Integrity, STA, Formal Verification, Synthesis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_46c163f2-a81"},"title":"R&D Engineering, Staff Engineer - Physical Design CAD","description":"You will be working at Synopsys, a leading provider of electronic design automation (EDA) software and services. As a Staff Engineer in the R&D Engineering team, you will be responsible for driving RTL-to-GDSII implementation for complex digital IP, ensuring signoff timing and PV closure. You will lead backend flow development, including PnR, STA, DRC, LVS, and EMIR analysis. You will collaborate with design, CAD, and cross-functional teams to optimize backend methodologies and resolve technical issues. You will also support project execution by troubleshooting timing, congestion, and physical verification challenges.
\nKey responsibilities include:
\nYou will be part of the dynamic Design Support Group (DSG) at Synopsys, a passionate collective of engineers dedicated to delivering world-class backend solutions. Our team thrives on innovation, collaboration, and a shared commitment to technical excellence. We work closely with customers and internal teams, supporting them through every stage of their design journey and continually pushing the boundaries of what's possible in digital backend technology.
\nAs a Staff Engineer, you will have the opportunity to work on cutting-edge projects, develop your technical skills, and contribute to the growth and success of the company. You will be part of a dynamic and supportive team that values innovation, collaboration, and technical excellence.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_46c163f2-a81","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-staff-engineer-physical-design-cad/44408/91852131072","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL-to-GDSII implementation","PnR","STA","DRC","LVS","EMIR analysis","backend flow development","physical verification","timing analysis","constraint management","timing closure strategies","EDA tools","scripting skills","version control","issue tracking","collaborative development environments"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:58.478Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDSII implementation, PnR, STA, DRC, LVS, EMIR analysis, backend flow development, physical verification, timing analysis, constraint management, timing closure strategies, EDA tools, scripting skills, version control, issue tracking, collaborative development environments"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a85bfb6-707"},"title":"Custom Analog Enablement and Methodology, Sr Staff Engineer","description":"Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.
\nAs a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.
\nKey responsibilities include:
\nThe ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.
\nThis role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_5a85bfb6-707","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/custom-analog-enablement-and-methodology-sr-staff-engineer-15402/44408/93442249536","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["custom analog layout design","sub-5nm FinFet/Gate-All-Around nodes","scripting languages: Tcl, Perl, Python","LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports"],"x-skills-preferred":["workflow automation and prototyping","collaboration with multiple organizations and teams across global time zones"],"datePosted":"2026-04-05T13:17:37.947Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"custom analog layout design, sub-5nm FinFet/Gate-All-Around nodes, scripting languages: Tcl, Perl, Python, LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports, workflow automation and prototyping, collaboration with multiple organizations and teams across global time zones"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b455ed20-1e0"},"title":"Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist","description":"We are seeking a highly skilled Applications Engineering, Sr Staff Engineer - RTL2GDS Application Specialist to join our team. As a key member of our Silicon Design & Verification team, you will be responsible for providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_b455ed20-1e0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/sunnyvale/applications-engineering-sr-staff-engineer-rtl2gds-application-specialist/44408/92176305600","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$157000-$235000","x-skills-required":["RTL to GDSII full flow","advanced node design methodologies","synthesis","physical design","static timing analysis","equivalence checking","parasitic extraction","DRC/LVS","power analysis"],"x-skills-preferred":["Perl","Tcl","Python","CAD automation methods","Design Compiler","ICC2","Fusion Compiler","Genus","Innovus","STA","IR drop analysis","Extraction","Formal verification"],"datePosted":"2026-03-06T07:26:03.775Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Sunnyvale, California"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL to GDSII full flow, advanced node design methodologies, synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, power analysis, Perl, Tcl, Python, CAD automation methods, Design Compiler, ICC2, Fusion Compiler, Genus, Innovus, STA, IR drop analysis, Extraction, Formal verification","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":157000,"maxValue":235000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_42cea958-a73"},"title":"Layout Design, Sr Engineer","description":"We are seeking a skilled Layout Design, Sr Engineer to join our team in Da Nang. As a Layout Design, Sr Engineer, you will be responsible for designing and integrating memory leafcells and standard cell layouts, optimizing layouts for speed, area, and power, and collaborating with circuit and verification engineers.
\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_42cea958-a73","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/layout-design-sr-engineer-in-da-nang/44408/91405850624","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","FinFET","DRC","LVS","ERC"],"x-skills-preferred":["Custom Compiler","ICV","Perl","Shell","TCL"],"datePosted":"2026-03-06T07:24:58.328Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, FinFET, DRC, LVS, ERC, Custom Compiler, ICV, Perl, Shell, TCL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a4f15f43-d71"},"title":"High-Speed SERDES Layout Specialist","description":"We are seeking a highly skilled High-Speed SERDES Layout Specialist to join our team. As a key member of our design team, you will be responsible for designing and implementing custom analog layout for high-speed SERDES blocks, including TX, RX, and PLLs, in advanced technology nodes.
\nWhat you'll do
\nWhat you need
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_a4f15f43-d71","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/high-speed-serdes-layout-specialist/44408/91299418752","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["custom analog layout","high-speed SERDES","floor planning","power grid design","signal routing","parasitic optimization","EDA tools","EMIR","DRC","LVS","ERC","ANT","ESD","DFM","PERC"],"x-skills-preferred":["package-level design","interposer and RDL layout"],"datePosted":"2026-03-06T07:22:03.742Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"custom analog layout, high-speed SERDES, floor planning, power grid design, signal routing, parasitic optimization, EDA tools, EMIR, DRC, LVS, ERC, ANT, ESD, DFM, PERC, package-level design, interposer and RDL layout"}]}