The role involves leading the complete subsystem lifecycle,from requirements gathering and architecture definition to final release phases. This includes crafting subsystem architectures, developing comprehensive functional specifications, defining and implementing micro-architectures, and driving RTL quality checks.

The ideal candidate will have a minimum of 8 years of hands-on experience in RTL design and subsystem architecture for complex ASIC/SoC projects. They should be proficient with standard protocols including PCIe, DDR, UFS, USB, and AMBA, and have demonstrated expertise in low power design methodologies and DFT architecture.

As a leader, the candidate will inspire and guide their peers, leveraging their experience to drive innovation, efficiency, and reliability. They should be committed to continuous learning, open to new perspectives, and value an inclusive workplace where ideas from all backgrounds contribute to groundbreaking solutions.

The role offers a comprehensive range of health, wellness, and financial benefits to cater to the needs of the employee. The total rewards include both monetary and non-monetary offerings.

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As a Senior Manager of SOC Engineering, you will oversee and drive end-to-end RTL design, verification, architecture, and integration of advanced subsystems. You will lead teams in Bangalore/Hyderabad, manage customer communications, and ensure timely, high-quality delivery. You will guide your team through the full lifecycle: from requirements to release, ensuring excellence at every stage. Foster innovation and continuous improvement, motivating engineers to reach their full potential.

Key Qualifications:

• Bachelor's or Master's in Electronics or related field, with 15+ years of overall experience
• 8+ years of hands-on techno-managerial experience managing remote and local teams
• Strong track record in Subsystem/SoC design, architecture, and implementation
• Deep expertise in Verilog/System Verilog and simulation tools
• Proficiency with interface protocols (AMBA APB/AXI/CHI, DDR, PCIe, Ethernet, USB, UFS, etc.)
• Experience with synthesis, lint, CDC, low power flows, and verification closure (SV UVM, BFM development, test environment creation)
• Outstanding communication skills and a passion for team development

What Sets You Apart:

• You have strong, hands-on technical experience and thrive on rolling up your sleeves to solve complex challenges
• You excel at turning high-level requirements into innovative solutions and see projects through to successful, timely completion
• You build strong, trust-based relationships with customers and stakeholders, always putting their needs at the centre
• You bring a creative mindset and lead proactively, inspiring your team to think big, embrace change, and drive continuous improvement

Hands-on experience is an absolute must for success in this role.

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Key responsibilities include:

• Developing and maintaining firmware for HID products
• Assisting in the generation of product specifications, test procedures, and qualification criteria
• Collaborating with cross-functional teams to realize HID programs from concept to implementation and into production

To succeed in this role, you will need to have a strong background in firmware development, excellent problem-solving skills, and the ability to work in a fast-paced environment.

We offer a competitive salary and benefits package, as well as opportunities for professional growth and development.

If you are a motivated and experienced Firmware Software Engineer looking for a new challenge, please submit your application.

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At Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.

Key Responsibilities:

• Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
• Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.
• Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.
• Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).
• Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.
• Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys' product lines.

Impact:

• Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.
• Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.
• Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys' tools, driving industry-leading outcomes.
• Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.
• Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.
• Strengthen Synopsys' position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.

Requirements:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.
• 5+ years of experience in chip design, EDA, or related fields.
• Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).
• Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.
• Solid understanding of Unix/Linux environments and design flow automation.
• Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.
• Familiarity with low power design techniques, computer architecture, and machine learning principles.

Who We're Looking For:

• A creative problem solver who approaches challenges with curiosity and resilience.
• An effective communicator who collaborates well with multidisciplinary teams.
• Detail-oriented with a passion for quality and continuous improvement.
• Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.
• Committed to learning, growth, and sharing knowledge with others.

The Team You'll Be A Part Of:

You'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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We are seeking a highly skilled and passionate engineer with a keen interest in advancing cutting-edge technology. With at least six years of experience in Physical Implementation (RTL-GDS), you bring deep expertise in autonomously diagnosing and resolving synthesis and place-and-route (PnR) challenges. Your proficiency in scripting languages such as Tcl, Python, Unix, and Perl complements your in-depth knowledge of Synopsys implementation tools and flows.

You will drive global customer adoption of Synopsys Implementation products, with a strong focus on RTL to GDS flows. You will deliver world-class customer service by providing enabling solutions and expert support for complex design implementation challenges. You will deeply analyze customer designs, debug issues, and deliver solutions through remote interface, in-house collaboration, or expert onsite visits for critical situations.

You will participate in and lead technical campaigns, including benchmarks, deployments, and solution enablement, to improve usability and drive adoption of new flows and technologies. You will advocate for customers by communicating their needs and feedback to product development teams, influencing the product roadmap and future technologies.

You will contribute technical articles to the Knowledge Base, offering front-line support and self-help guidance for common customer challenges. You will roll out new product methodologies by providing training, hands-on guidance, and ongoing technical support to customers.

The impact you will have is delivering comprehensive technical solutions and support in key customer flagship projects, ensuring successful tape-outs and project milestones. You will lead the deployment of new flows to achieve better PPA (Power, Performance, Area) and improve block-level ownership activities for enhanced QoR (Quality of Results). You will play a pivotal role in enabling new technology nodes and advancing customer design methodologies.

You will drive innovation by addressing design challenges, improving product performance based on customer feedback, and collaborating with R&D on future technologies. You will promote Synopsys tools and solutions to grow market presence and ensure seamless transitions for customers adopting EDA solutions. You will strengthen Synopsys' reputation as a trusted partner and thought leader in the semiconductor industry.

What You'll Need:

• B-Tech or equivalent with a minimum of 6+ years of experience, or M-Tech or equivalent with at least 5+ years of experience in semiconductor design and implementation.
• Expertise in Implementation Methodologies, Physical Design, and hands-on experience with Synopsys tools such as Fusion Compiler or ICC-II (or equivalent tools).
• Thorough understanding of RTL to GDS flows and methodologies, with deep domain knowledge in Synthesis, Place & Route, and timing analysis.
• Hands-on experience in scripting (TCL, Python, Unix, Perl) for automation, tool integration, and debugging.
• Experience in multiple chip tape-outs, preferably at 7nm or lower technology nodes across various foundries.
• Knowledge of STA, Low Power Flows, Design Planning, and prior customer-facing roles is a strong advantage.
• Excellent verbal and written communication skills, with a proven track record of engaging with customers and internal teams.

Who You Are:

• Excellent communicator able to build trust and rapport with diverse stakeholders.
• Analytical thinker with strong troubleshooting and debugging skills.
• Customer-centric, empathetic, and proactive in anticipating and meeting customer needs.
• Highly collaborative team player who thrives in fast-paced, multicultural environments.
• Self-motivated, innovative, and passionate about continuous learning and process improvement.
• Adaptable and resilient, able to manage multiple priorities and evolving technical landscapes.

The Team You’ll Be A Part Of:

You will join a dynamic, expert team within the Silicon Design & Verification business at Synopsys, based in Hyderabad. The team is dedicated to driving customer success in high-impact projects, deploying advanced implementation flows, and shaping the future of silicon design. Collaboration, technical excellence, and a commitment to innovation are at the core of our culture. You’ll work closely with customers, R&D, and field teams to deliver transformative solutions and advance industry-leading technologies.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies.

• Reviewing and analyzing floorplans and intricate circuits with circuit designers.

• Running complete sets of design verification tools available on AMS blocks.

• Working with the circuit design team to plan/schedule work and coordinate vital layout tradeoffs as needed.

• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.

• Exceeding engineering specifications and expectations by working closely with the circuit design team.

What you need

• B.Tech/M.Tech with 5+ years of relevant experience.

• Proven experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.

• Experience in implementing analog layouts to achieve tight matching, low noise, and low power consumption.

• High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.

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What you'll do

• Developing and delivering RTL designs for High Bandwidth Memory (HBM) PHY IP, working at the intersection of digital, mixed-signal, and analog domains.
• Translating architectural requirements and industry standard specifications into robust, high-performance RTL implementations using SystemVerilog and Verilog.

What you need

• 7-10 years of hands-on experience in RTL design, including significant work on high-speed digital and mixed-signal interfaces.
• Expertise in SystemVerilog and Verilog for RTL development.

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What you'll do

You will lead the NVM TestChip and IP design flow across multiple technologies and foundries, ensuring robust and scalable solutions for diverse applications.

• Architecting, designing, and verifying CMOS-based non-volatile memory IP modules, from concept to production tapeout.
• Collaborating with product engineers to perform silicon verification, in-depth testing, and debugging to validate IP performance on silicon.
• Conducting post-layout extraction, simulation, and comprehensive testing in conjunction with silicon validation teams.

What you need

• 5–12+ years of industry experience in circuit design, with a strong emphasis on analog circuit design and analysis; memory design experience is a significant plus.
• Deep understanding of layout considerations for advanced nodes, including parasitic effects, matching techniques, and signal integrity.
• Expertise in electrical problem-solving, including root cause analysis of circuit failures and development of effective solutions.
• Hands-on experience with TestChip tapeout flows, silicon debugging (FIB, micro-probing, post-layout RC extraction), and statistical design methodologies (e.g., Monte-Carlo analysis).
• Strong transistor-level analog design skills, including sense-amplifier, charge pump, high voltage regulator, and bandgap reference circuit design.
• Proficiency with circuit simulation tools (HSIM, HSPICE, etc.) and custom schematic/layout editors (e.g., Custom Compiler).
• Experience with low power design, power management circuitry, and FinFET design is a plus.

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