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This role is metrology-focused but also has strong interaction with tooling design, fabrication, fixture setup and periodic inspection support activities.</p>\n<p>The ideal candidate brings hands-on metrology experience, is comfortable working in a manufacturing and tooling environment and enjoys collaborating with Engineering and Production teams to ensure that tooling and aircraft components meet engineering and aerodynamic requirements.</p>\n<p>You will use advanced measurement technologies,including laser trackers, 3D scanners, and metrology arms,to verify tooling and aircraft components, support Production activities and provide clear analytical feedback to internal customers both in written and verbal forms.</p>\n<p>Key responsibilities include:</p>\n<p>Performing dimensional measurement and verification of tooling, fixtures, jigs, and aircraft components using laser trackers, portable metrology arms, and 3D scanning systems. Collecting, analysing and interpreting measurement data to verify conformance to engineering drawings, aerodynamic specifications and CAD models. Generating clear analytical and graphical inspection reports for Engineering and production stakeholders. Supporting development of measurement strategies, including selecting appropriate metrology equipment and methods for Tooling and specific applications. Maintaining and monitoring metrology equipment to ensure accuracy, calibration and operational readiness.</p>\n<p>Additionally, you will provide hands-on support of tooling build, assembly and adjustment activities for tight-tolerance fixtures and tooling systems, assist Production teams with fixture setup, alignment, and troubleshooting, collaborate with Tooling machinists, Engineers, and Production personnel to develop practical measurement and tooling solutions, and work with limited supervision while managing assigned measurement and support activities.</p>\n<p>What you will learn includes advanced aerospace metrology techniques and best practices, tooling build philosophies and manufacturing processes, measurement data analysis and interpretation, and use of multiple metrology systems and CAD platforms in a production environment.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_51539399-f02","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Honda Aircraft Company","sameAs":"https://careers.honda.com","logo":"https://logos.yubhub.co/careers.honda.com.png"},"x-apply-url":"https://careers.honda.com/us/en/job/10528/Engineer-Tooling-Metrologist","x-work-arrangement":"onsite","x-experience-level":"entry|mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["metrology","laser trackers","3D scanners","metrology arms","GD&T","CAD platforms","CATIA V5","traditional measurement tools","calipers","micrometers","gage blocks","surface plates"],"x-skills-preferred":["Verisurf","Spatial Analyzer","GOM","Geomagic"],"datePosted":"2026-04-22T17:23:00.702Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Greensboro"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Automotive","skills":"metrology, laser trackers, 3D scanners, metrology arms, GD&T, CAD platforms, CATIA V5, traditional measurement tools, calipers, micrometers, gage blocks, surface plates, Verisurf, Spatial Analyzer, GOM, Geomagic"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_76c9a01c-58a"},"title":"Data Center Portfolio Planning & Execution Lead","description":"<p>We&#39;re looking for a Data Center Portfolio Planning &amp; Execution Lead to drive the planning and framework that ensures every site moves smoothly from the front-end phases through design, construction, equipment delivery, commissioning, and operational readiness.</p>\n<p>This role owns the portfolio-level operating system: translating capacity supply pipeline into integrated project plans that span every phase of delivery, building the tooling and automation that runs it at scale, and maintaining Anthropic&#39;s datacenter capacity catalog , a lifecycle view of our fleet that supports both execution orchestration and steady-state capacity planning.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Manage the integrated master plan for each site across the portfolio , stitching power ramp, design, construction, sourcing, deployment, and operations readiness into a single coordinated schedule with clear milestones and dependencies</li>\n<li>Develop and maintain Anthropic&#39;s datacenter catalog for deployed and in-progress capacity. Manage the portfolio-level view of physical infrastructure &amp; cluster interfaces across all sites and partners to enable planning decisions such as equipment fungibility, accelerator platforms, tech insertion, or workload allocation</li>\n<li>Define and run the stage gates and decision locks for cluster delivery , from lease execution to design lock through procurement, construction, equipment installation, commissioning, and handover</li>\n<li>Drive gate reviews, manage exceptions, and track the downstream impact of deviations across the portfolio</li>\n<li>Manage portfolio reviews and risk tracking for DC Infra leadership and Compute Supply</li>\n</ul>\n<p>Tooling &amp; process:</p>\n<ul>\n<li>Develop tooling and automation to enable cross-functional planning flow-down from datacenter capacity availability dates</li>\n<li>Partner with Design, Supply Chain, Construction, and DC Ops program leads to drive cross-pillar process improvements as portfolio scales</li>\n</ul>\n<p>You may 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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15231</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>02/15/2026</p>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong></p>\n<ul>\n<li>An experienced and passionate Analog and Mixed-Signal (A&amp;MS) Senior Circuit Design Expert with a strong background in PLL , data converters and SERDES design.</li>\n</ul>\n<ul>\n<li>You have a deep understanding of mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction.</li>\n</ul>\n<ul>\n<li>Your expertise includes circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes.</li>\n</ul>\n<ul>\n<li>You excel in developing Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology.</li>\n</ul>\n<ul>\n<li>You thrive in collaborative environments, working closely with silicon test and debug experts to advance quality through Sim2Sil correlation.</li>\n</ul>\n<ul>\n<li>You are also passionate about building and nurturing key analog design talent to grow business impact through successful project execution.</li>\n</ul>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Leading NRZ/PAM4 Serdes analog design transceiver solutions.</li>\n</ul>\n<ul>\n<li>Developing Analog Full custom circuit macros for High Speed PHY IP in advanced technology nodes.</li>\n</ul>\n<ul>\n<li>Collaborating with silicon test and debug experts for Sim2Sil correlation.</li>\n</ul>\n<ul>\n<li>Analyzing various mixed signal techniques for power reduction, performance enhancement, and area reduction.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Driving innovation in mixed-signal advanced analog serdes design.</li>\n</ul>\n<ul>\n<li>Enhancing the performance and efficiency of high-speed physical interfaces.</li>\n</ul>\n<ul>\n<li>Contributing to the development of cutting-edge technology in High Speed PHY IP.</li>\n</ul>\n<ul>\n<li>Improving quality and robustness of design through collaboration and Sim2Sil correlation.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BE 15+ years of relevant experience or MTech 12+ years of relevant experience in mixed signal analog, clock, and datapath circuit design.</li>\n</ul>\n<ul>\n<li>Experience in designing Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits.</li>\n</ul>\n<ul>\n<li>Knowledge in Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity .</li>\n</ul>\n<ul>\n<li>Knowledge of RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Strong fundamentals of CMOS, device physics, and sub-micron design methodologies.</li>\n</ul>\n<ul>\n<li>Experience with PLL designs and high-speed digital circuit design.</li>\n</ul>\n<ul>\n<li>Knowledge of control systems, band gaps, bias, op-amps, LDOs, and feedback techniques.</li>\n</ul>\n<ul>\n<li>Familiarity with digitally assisted analog circuit techniques.</li>\n</ul>\n<ul>\n<li>Capable to drive technical decision and tradeoff with customer focus</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join our High-Performance Computing (HPC) Enterprise analog/mixed-signal Serdes team involved in cutting-edge High Speed PHYSICAL Interface Development.</p>\n<p>You will work with experienced teams locally and with colleagues from various sites across the globe, fostering a collaborative and innovative environment.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p><strong>Get an idea of what your daily routine <strong>around the office</strong> can be like</strong></p>\n<p>\\ Explore <strong>Noida</strong></p>\n<p>View Map</p>\n<p>---</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_de112d07-e65","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-design-principal-engineer/44408/91802916768","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert","PLL , data converters and SERDES design","mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction","circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes","Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology","silicon test and debug experts to advance quality through Sim2Sil correlation","Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits","Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity ","RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters"],"x-skills-preferred":[],"datePosted":"2026-03-09T11:06:28.077Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog and Mixed-Signal (A&MS) Senior Circuit Design Expert, PLL , data converters and SERDES design, mixed-signal techniques for dynamic and static power reduction, performance enhancement, and area reduction, circuit architectures simulation, circuit layout, and knowledge of bipolar, CMOS, passive network and interconnect parasitic impact in advanced finfet technology nodes, Analog Full custom circuit macros, such as PLLs, Clock Path Functions, clocking solutions, TX/RX datapaths, and power management and regulation for High Speed PHY IP, in both planar and fin-fet CMOS technology, silicon test and debug experts to advance quality through Sim2Sil correlation, Charge-pump-based PLLs, Fractional-N PLLs, Digital PLLs, XTAL oscillators, and LO generation circuits, Equalizers , CDR architectures , high-speed digital circuit design , timing/phase noise analysis, signal integrity , RF architecture and blocks such as transceivers front-end , VCOs, LNA, and up/down converters"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_dfb98ecf-dd6"},"title":"Engineering Architect (Analog Mixed-Signal Architect)","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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Above all, you are driven by the opportunity to contribute to critical components powering AI systems, knowing your work has a lasting impact on the future of technology.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Reviewing and integrating the latest multichip and interposer technologies from various foundries into Synopsys’ HBM PHY products.</li>\n</ul>\n<ul>\n<li>Defining bump maps and top-level floorplans for HBM PHY products to ensure optimal performance, power, and area (PPA).</li>\n</ul>\n<ul>\n<li>Collaborating with layout teams to deliver top metal covercells optimized for performance and reliability in HBM PHY designs.</li>\n</ul>\n<ul>\n<li>Working with layout and SIPI teams to design interposer geometries that maximize performance and signal integrity.</li>\n</ul>\n<ul>\n<li>Mentoring junior engineers and providing technical guidance across multi-site teams.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Elevate the performance and reliability of Synopsys’ HBM PHY products, directly contributing to the advancement of AI and high-performance computing systems.</li>\n</ul>\n<ul>\n<li>Enable successful integration of cutting-edge multichip and interposer technologies, ensuring Synopsys remains at the forefront of semiconductor innovation.</li>\n</ul>\n<ul>\n<li>Improve manufacturability and scalability of memory interface IPs, supporting the needs of leading semiconductor companies worldwide.</li>\n</ul>\n<ul>\n<li>Drive technical excellence across cross-functional teams, fostering collaboration and knowledge sharing.</li>\n</ul>\n<ul>\n<li>Enhance customer satisfaction by delivering robust, high-quality solutions that meet demanding market requirements.</li>\n</ul>\n<ul>\n<li>Support Synopsys’ reputation as a trusted IP provider through leadership, innovation, and problem-solving.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>MS or PhD in Electrical Engineering or related field.</li>\n</ul>\n<ul>\n<li>15+ years of experience in memory or die-to-die interface design.</li>\n</ul>\n<ul>\n<li>Expertise in floorplan optimization for IPs integrating full-custom analog and synthesized digital blocks.</li>\n</ul>\n<ul>\n<li>Strong experience with power grid design and EMIR analysis.</li>\n</ul>\n<ul>\n<li>Proficiency in interposer design and implementation.</li>\n</ul>\n<ul>\n<li>Solid understanding of analog principles and designs (bandgaps, LDO regulators, current mirrors, DLL/PLLs).</li>\n</ul>\n<ul>\n<li>Deep knowledge of signal-integrity and power integrity principles.</li>\n</ul>\n<ul>\n<li>Experience with layout impact on circuit performance and reliability.</li>\n</ul>\n<ul>\n<li>Ability to troubleshoot and debug memory interfaces effectively.</li>\n</ul>\n<ul>\n<li>Excellent communication and collaboration skills across multi-site teams.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>A collaborative leader who inspires and guides teams to technical excellence.</li>\n</ul>\n<ul>\n<li>Detail-oriented, analytical, and able to balance multiple priorities.</li>\n</ul>\n<ul>\n<li>Innovative thinker, open to new approaches and emerging technologies.</li>\n</ul>\n<ul>\n<li>Effective communicator, capable of translating complex technical concepts for diverse audiences.</li>\n</ul>\n<ul>\n<li>Resilient and proactive in addressing challenges and driving solutions.</li>\n</ul>\n<ul>\n<li>Committed to continuous learning and professional growth.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>You’ll join our High Bandwidth Memory interface design team, a group of passionate engineers dedicated to developing best-in-class IP for the world’s most advanced computing systems. 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