The successful candidate will join a global team responsible for designing and developing Equities Volatility, Risk, PnL, and Market Data systems.

You will work hands-on with other developers, QA, and production support, and will partner closely with Portfolio Managers, Middle Office, and Risk Managers.

We are looking for a very strong senior engineer with deep knowledge of equity derivatives products and their pricing and risk characteristics.

You must be a highly capable hands-on developer with a solid understanding of front-to-back trading system workflows, especially pricing and risk.

Excellent communication skills, strong ownership, and the ability to work effectively in a fast-paced, collaborative environment are essential.

Experience in Unix/Linux environments is required; exposure to cloud and containerization technologies is a plus.

Principal Responsibilities

• Design, build, and maintain real-time equity derivatives pricing and risk systems (including volatility and PnL components).

• Implement robust, scalable, and low-latency server-side components in a multi-threaded environment.

• Collaborate with portfolio managers, risk, and middle office to translate business requirements into technical solutions.

• Contribute to UI components as needed (and learn new UI technologies where required).

• Write clear technical documentation and maintain system design and support guides.

• Develop and execute automated tests using approved frameworks; ensure production quality and reliability.

• Provide level-3 support, troubleshooting, and performance tuning for production systems.

Qualifications & Skills

• 7+ years of professional experience as a server-side software engineer.

• Deep understanding of equity derivatives products (options, volatility products, exotics) and their pricing and risk measures (e.g., Greeks, PnL attribution).

• Strong experience with concurrent, multi-threaded, and low-latency application architectures.

• Expertise in Object-Oriented design, design patterns, and best practices in unit and integration testing.

• Experience with distributed caching and replication technologies.

• Solid knowledge of Unix/Linux environments is required.

• Experience with Agile/Scrum development methodologies is required.

• Exposure to front-end/UI technologies (JavaScript, HTML5) is a plus.

• Experience with cloud platforms and containerization (e.g., Docker, Kubernetes) is a plus.

• B.S. in Computer Science, Mathematics, Physics, Financial Engineering, or related field.

• Demonstrates thoroughness, attention to detail, and strong ownership of deliverables.

• Effective team player with a strong willingness to collaborate and help others.

• Strong written and verbal communication skills; able to explain complex technical and quantitative topics to non-technical stakeholders.

• Proven ability to write clear, concise documentation.

• Fast learner with the ability to adapt to new technologies and business domains.

• Able to perform under pressure, work with ambitious team members, and handle changing priorities.

Millennium pays a total compensation package which includes a base salary, discretionary performance bonus, and a comprehensive benefits package.

The estimated base salary range for this position is $175,000 to $250,000, which is specific to New York and may change in the future.

When finalizing an offer, we take into consideration an individual’s experience level and the qualifications they bring to the role to formulate a competitive total compensation package.

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As a Senior Software Engineer, C++ Software Integration, you will design, implement, and maintain C++ and Python software in support of complex, cross-platform systems. You will contribute to system architecture with a focus on performance, maintainability, and integration. You will develop and support APIs and messaging interfaces, integrate third-party software and hardware systems, including real-time and simulation tools. You will debug and support distributed systems, with attention to threading, timing, and data flow. You will apply modern agile practices such as test-driven development, continuous integration, and automated testing. You will improve and maintain CI/CD workflows using tools like GitLab CI, Docker, CMake, and Conan. You will collaborate across teams and projects to share solutions and promote good software practices. You will continuously learn and adapt to new tools, standards, and technologies.

This position is ideal for a C++ generalist who thrives on tackling complex challenges in systems and systems integration. If you enjoy building cross-language software, improving CI/CD pipelines, and integrating distributed real-time systems, you'll find this role rewarding.

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As a Security Engineer, you will be the technical authority on how Saronic builds, ships, and runs secure software. You will lead secure code review, SAST, DAST, and fuzzing efforts, and define secure coding standards for Rust development including memory safety practices, safe FFI boundaries, and secure error handling.

You will conduct threat modeling for software systems and translate findings into actionable security requirements integrated into design reviews and sprint planning. You will drive vulnerability management for software dependencies, including tracking, prioritization, and remediation of vulnerabilities in third-party crates and libraries.

You will secure and harden NixOS configurations for vessel platforms and development infrastructure, leveraging Nix's reproducibility and declarative model for security enforcement. You will design system hardening profiles in NixOS including kernel hardening, service isolation, mandatory access controls, and minimal attack surface configurations.

You will define and enforce package management and dependency policies within the Nix ecosystem, ensuring build closures are auditable, reproducible, and free from unauthorized or vulnerable packages. You will architect secure system update and rollback mechanisms using NixOS capabilities, ensuring fleet-wide consistency and integrity.

You will design and implement security controls across the CI/CD pipeline including source integrity, build isolation, artifact signing, and deployment verification with build environments that are ephemeral, isolated, and hardened.

You will build and maintain software supply chain security practices aligned to SLSA framework principles, including provenance tracking, hermetic builds, signed attestations, and SBOM generation.

You will integrate security scanning (SAST, SCA, container scanning, secrets detection) into CI/CD pipelines as automated guardrails, and create self-service pipeline templates that enable teams to ship without bottlenecks.

You will design secure deployment patterns for vessel software updates, including secure delivery, integrity verification, and rollback capabilities.

You will implement runtime application security controls including logging, monitoring, and anomaly detection for deployed services.

You will define software and systems security standards, patterns, and reference architectures that engineering teams adopt as the default secure path.

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As a Senior Staff Engineer in RTL Design and Verification, you will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects. You will develop comprehensive test cases to ensure robust product functionality and performance.

You will collaborate with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis. You will stay current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.

You will contribute to the improvement of verification methodologies and automation flows. You will document design specifications, verification plans, and results to ensure transparency and repeatability.

You will participate in code reviews and technical discussions to drive innovation and continuous improvement.

You will accelerate the development of industry-leading SLM IPs that power the world's top technology companies. You will enhance product reliability, performance, and user experience for global semiconductor solutions.

You will drive innovation in verification methodologies, setting new standards for efficiency and accuracy. You will enable successful integration of advanced 3D-IC technologies, expanding Synopsys' leadership in the market.

You will foster strong customer relationships through technical expertise and responsive support. You will contribute to a culture of excellence and continuous learning within the engineering team.

To succeed in this role, you will need a BS/MS in Computer Science, Electrical Engineering, or related field. You will require 8+ years of hands-on experience in RTL design and verification.

You will need proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies. You will need experience working in Unix/Linux environments.

You will need strong debugging and problem-solving skills, especially in complex chip design environments. You will need excellent written and verbal communication skills in English.

Knowledge of digital, analog, and mixed-signal IP/circuit design is a plus. Familiarity with 3D-IC standards and semiconductor verification best practices is desirable.

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Key responsibilities include:

• Defining, validating, and enabling complex multi-rack FPGA-based systems to support cutting-edge hardware development.
• Developing and optimizing RTL code for Xilinx UltraScale, UltraScale+, and Versal FPGAs to ensure maximum performance and reliability.
• Driving the development and integration of hardware emulation strategies on leading FPGA platforms such as Zebu and HAPS.
• Mapping RTL designs into FPGA environments, utilizing deep verification and implementation knowledge to facilitate smooth prototyping and validation.
• Generating and packaging diagnostic tests for both production and field use, ensuring robust system performance and rapid troubleshooting.

As a Staff Hardware Engineer, you will work closely with cross-functional teams to accelerate the development of next-generation technologies through advanced FPGA design and integration. You will strengthen team productivity and knowledge by actively collaborating, mentoring, and sharing expertise with colleagues.

Requirements include:

• BS/MS in Computer Science, Electrical Engineering, or a related field.
• 5+ years of hands-on experience in RTL design and verification, preferably with complex FPGA systems.
• Proficiency in Hardware Description Languages such as VERILOG, VHDL, or SystemVerilog.
• Expertise in using industry-standard EDA tools and methodologies for design and verification.
• Hands-on experience with FPGA flows and tools like Vivado, and familiarity with Unix/Linux environments.
• Experience with scripting languages (Shell, Perl, Python, TCL) for automation and productivity enhancement.
• Background in HDL simulation, emulation, and prototyping platforms (e.g., Zebu, HAPS).
• Strong logical thinking and problem-solving abilities, with a keen attention to detail.

Benefits include:

• Comprehensive medical and healthcare plans that work for you and your family.
• In addition to company holidays, we have ETO and FTO Programs.
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
• Save for your future with our retirement plans that vary by region and country.
• Competitive salaries.

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Your primary focus will be on ensuring the seamless installation and maintenance of Synopsys hardware, directly contributing to customer satisfaction and success. You will also improve hardware reliability and performance through meticulous analysis and corrective action implementation, support the continuous improvement of production processes, and facilitate the integration of hardware into complete systems.

To succeed in this role, you will need a minimum of 5+ years of related experience in test and validation engineering, proficiency in Linux environments and scripting languages such as bash and tcsh, experience with hardware installation and maintenance at customer sites, strong analytical skills to identify and resolve hardware issues, and a willingness to travel both domestically and internationally.

As a detail-oriented and highly organized individual with excellent communication skills, you will be able to work collaboratively across teams, adapt to diverse work environments, and thrive in a customer-centric approach. Your passion for technology and innovation will drive your success in this role.

In return, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs, including both monetary and non-monetary offerings.

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At Synopsys, we're seeking a Staff Engineer (Machine Learning) to join our Machine Learning Center of Excellence (ML CoE) within our Silicon Design & Verification business. As a key member of this highly innovative team, you'll be responsible for designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.

Key Responsibilities:

• Designing and developing machine learning-based optimization applications for advanced chip design, spanning architectural through physical design levels.
• Integrating ML-driven solutions into a variety of EDA tools, building on the success of DSO.ai and expanding beyond physical implementation.
• Automating chip design flows with scripting languages (Perl, Python, Tcl, shell scripts) to increase efficiency and reproducibility.
• Collaborating with cross-functional teams to identify design bottlenecks and propose innovative solutions for enhancing power, performance, and area (PPA).
• Conducting research and prototyping novel chip design methodologies, demonstrating new concepts, and driving them to productization.
• Staying current with industry trends in silicon design, machine learning, and EDA, and championing their adoption within Synopsys' product lines.

Impact:

• Accelerate the development of next-generation silicon chips by enabling smarter, faster design optimization through AI and machine learning.
• Reduce time-to-market for customers by eliminating months off project schedules, directly impacting their competitiveness.
• Enhance the performance, power efficiency, and cost-effectiveness of chips designed with Synopsys' tools, driving industry-leading outcomes.
• Shape the evolution of EDA software by pioneering ML-driven methodologies adopted by semiconductor leaders worldwide.
• Enable customers to autonomously explore vast design spaces, achieving optimal results with reduced manual intervention.
• Strengthen Synopsys' position as the global leader in silicon design and verification by delivering innovative, high-impact solutions.

Requirements:

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related discipline.
• 5+ years of experience in chip design, EDA, or related fields.
• Expertise in at least one domain of chip design (architectural, micro-architectural, RTL, circuit, or physical design).
• Strong programming and automation skills using Perl, Python, Tcl, or shell scripting.
• Solid understanding of Unix/Linux environments and design flow automation.
• Knowledge of industry-standard RTL design, synthesis, place and route, verification, ATPG, custom-circuit design, and signoff flows.
• Familiarity with low power design techniques, computer architecture, and machine learning principles.

Who We're Looking For:

• A creative problem solver who approaches challenges with curiosity and resilience.
• An effective communicator who collaborates well with multidisciplinary teams.
• Detail-oriented with a passion for quality and continuous improvement.
• Self-driven, adaptable, and comfortable with ambiguity in fast-paced environments.
• Committed to learning, growth, and sharing knowledge with others.

The Team You'll Be A Part Of:

You'll join the Machine Learning Center of Excellence (ML CoE) within Synopsys' Silicon Design & Verification business. This highly innovative team is at the forefront of integrating AI and ML into chip design, collaborating with experts across architecture, implementation, and verification. Together, you'll drive the development of ML-based design optimization solutions and set new standards for the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Responsibilities:

• Architect power delivery systems for data center and super compute platforms, including multiphase VRMs and Intermediate Bus Converters (IBCs).
• Architect low voltage, high current (500A-1000A+) power rails for LPU, GPU and accelerator modules.
• Apply control theory principles to optimize power converter performance, stability, and transient response.
• Select and characterize power components including MOSFETs, inductors, transformers, and magnetic devices using vendor tools and configuration GUIs.
• Collaborate with ASIC and package teams to ensure power integrity across high-density PCB builds.
• Develop and complete lab validation plans using oscilloscopes and other test equipment.
• Build automation scripts to improve characterization efficiency and data analysis.
• Collaborate with power management ICs via I2C, SPI, and PCIe protocols for system integration and debug.
• Work with cross-functional teams including mechanical, thermal, firmware, and silicon build engineers.

Requirements:

• BS or MS in Electrical Engineering (or equivalent experience) with focus on power electronics.
• 5+ years of experience crafting power systems for data center, super compute, or high-performance computing applications.
• Deep expertise in multiphase VRM development and Intermediate Bus Converter (IBC) topologies, and control theory as applied to power converters.
• Hands-on experience with high-current (500A-1000A+) low voltage power delivery systems.
• Proficiency with Cadence tools for power integrity analysis and simulations, and experience with high-density PCB build and layout considerations.
• Familiarity with communication interfaces: I2C, SPI, PCIe.
• Proficient with scripting languages (Python, Perl) and Linux environment.
• Strong hands-on lab skills with oscilloscopes and power measurement equipment.
• Clear and effective communication skills, both written and verbal.

Preferred Qualifications:

• Experience with AI accelerator power delivery for platforms such as TPU, GPU, or similar architectures.
• Knowledge of advanced magnetic component build and optimization for high-density applications.
• Experience with power modeling and simulation tools.
• Background in EMI/EMC compliance and mitigation techniques.
• Proven track record in bringing power solutions from concept to mass production with experience collaborating with external vendors and suppliers.

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You will have the opportunity to work in a dynamic R&D Centre, collaborating with expert teams to create great products in video conference cameras. Passion for design and development is the key, this includes creating and testing solutions to meet design goals.

Your Contribution:

• Contribute to the development of cutting-edge camera image processing algorithms, including Noise Reduction, Sharpening, Tone Mapping, and Scaling.
• Collaborate on the subjective assessment of image and video quality, leveraging your expertise to test, measure, and evaluate imaging and video outputs.
• Work closely with cross-functional teams to gather insights and enhance the overall visual quality of Logitech's video solutions.

Key Qualifications:

• Educational Requirements: Working towards an M.S. or Ph.D. degree in Computer Science, Electrical Engineering, or a related field with a concentration in Image Processing at the start of the internship.
• Have taken a Computational Imaging course, or possess solid understanding of Image signal processing fundamentals (Bayer pipeline, demosaic, noise reduction, color correction, sharpening, tone mapping, etc.) and theoretical foundations.
• Experience with C/C++ (or embedded C) for algorithm and systems development on Linux or embedded platforms.
• Knowledge and experience in image quality assessment techniques, including metrics for evaluating image fidelity, sharpness, and color accuracy.
• Curiosity and a hands-on mindset toward bridging software and hardware, with an eagerness to experiment and iterate.
• Strong communication and collaboration skills; comfortable working across hardware, firmware, and algorithm teams in a collaborative working environment.
• A strong curiosity, self-motivation, and a passion for solving complex, open-ended challenges.
• Comfortable navigating the uncertainties and dynamic nature of early-stage product development. Ability to adapt quickly and thrive in a fast-paced environment.

In addition, preferable skills and behaviours include:

• Experience with camera software development on Android platforms.
• Familiarity with Linux environments and the ability to work comfortably within them.
• A strong understanding of digital video technologies, including formats, and processing workflows.
• Experience in AI/ML, mainly computer vision techniques and algorithms.
• Exceptional organisational skills, with a keen attention to detail and the ability to manage tasks systematically.
• A personable and easy-going demeanour, with the ability to work comfortably in a collaborative team environment.
• A genuine passion for design and technology, with a keen interest in innovative solutions.
• A love for cameras/photography and an enthusiasm for advancing the field of imaging technology.

Compensation:

This position offers an hourly rate typically between $47.00 hourly- $49.00 hourly commensurate to the level of degree program in which an applicant is actively enrolled.

Logitech offers interns benefits of Paid Holidays, and access to Employee Product Discounts.

#LI-SN1

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We are the Audi Revolut F1 Team.

Audi will compete in the FIA Formula 1 World Championship starting in 2026.

The team has three locations. Audi's Motorsport Competence Center in Neuburg, Germany, is considered one of the most modern of its kind in Europe.

The Formula 1 Factory of Audi Motorsport AG in Hinwil (Switzerland) is known for its innovative technologies and passion for racing.

The Audi Motorsport Technology Centre, UK, is in its launch phase and growing continuously. Our power unit comes from Neuburg, while Hinwil is responsible for chassis development and race operations.

Your mission

• Contribute to the overall CFD process development in an F1 environment
• Have an impact on how CFD technology is used by the whole aerodynamic department
• Improve the CFD physical modelling to increase the accuracy of the prediction
• Work closely with external software providers on specific development projects
• Help us set future directions and trends in advanced CFD methods
• Work in an agile software development team

Your profile

• MSc or PhD in Aerospace Engineering, Mechanical Engineering, Mathematics or a related field with a strong focus on computational fluid dynamics
• At least 3 years of professional experience developing CFD Methods in OpenFOAM
• Previous F1 experience will be considered a plus
• Knowledge of high-Reynolds flows physics and turbulence modelling
• Knowledge of C++ and Python programming languages
• Familiarity with software release, update and deployment techniques
• Experience in parallel computing and high-performance computing (HPC)
• Familiarity with developing software in Linux environments
• Hard-working, independent and reliable
• Self-motivating, responsible and meticulous
• Open to share a continuous learning culture within the team
• Promote a collaborative, respectful and trusting work environment within the team
• Proficiency in English language skills. German language skills will be an advantage

Driven by passion.

Every lap is a statement, every start a promise. This is what defines us.

Take a closer look.

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Explore the R26

Meet the team

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What you'll do

• Providing advanced technical debugging support for Totem-SC and Totem, ensuring seamless customer experiences.
• Setting up, validating, and reproducing customer flows to investigate and resolve complex issues.
• Collaborating with R&D teams to perform root cause analysis and implement effective solutions.
• Supporting certification and evaluation flows for analog IP and power integrity tools.
• Delivering on-site or remote technical support to Korean customers, adapting to their unique needs and environments.
• Extending support to global customers as needed, contributing to Synopsys' worldwide reputation for excellence.

What you need

• Strong understanding of analog IP EM/IR analysis methodologies and challenges.
• Hands-on experience with power integrity tools such as Totem and Totem-SC.
• Proficiency in SPICE simulation and netlist debugging for analog and mixed-signal designs.
• Knowledge of DSPF/SPF formats and their application in power and signal integrity analysis.
• Expertise in Linux environments, with scripting skills in Python or TCL preferred.
• Familiarity with foundry PDKs and certification flows for advanced semiconductor processes.

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What you'll do

• Providing advanced technical debugging support for Totem-SC and Totem, ensuring seamless customer experiences.
• Setting up, validating, and reproducing customer flows to investigate and resolve complex issues.
• Collaborating with R&D teams to perform root cause analysis and implement effective solutions.
• Supporting certification and evaluation flows for analog IP and power integrity tools.
• Delivering on-site or remote technical support to Korean customers, adapting to their unique needs and environments.
• Extending support to global customers as needed, contributing to Synopsys' worldwide reputation for excellence.

What you need

• Strong understanding of analog IP EM/IR analysis methodologies and challenges.
• Hands-on experience with power integrity tools such as Totem and Totem-SC.
• Proficiency in SPICE simulation and netlist debugging for analog and mixed-signal designs.
• Knowledge of DSPF/SPF formats and their application in power and signal integrity analysis.
• Expertise in Linux environments, with scripting skills in Python or TCL preferred.
• Familiarity with foundry PDKs and certification flows for advanced semiconductor processes.

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What you'll do

• Managing one or multiple Mixed-Signal IP projects from concept to customer delivery.
• Representing the product line both internally and externally, ensuring clear communication of project status to key customers.

What you need

• A degree in Engineering or Applied Science (or equivalent) with 8+ years of relevant experience.
• Proven experience in communicating with and managing customer expectations.

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What you'll do

• Partner with cross-functional engineering, product, and business teams to define project scope, requirements, and success criteria.
• Develop and maintain comprehensive project plans, including schedules, resource allocation, dependencies, and risk mitigation strategies.

What you need

• A degree in Engineering, Applied Science, or equivalent practical experience.
• 10+ years of experience in customer-facing project or program management roles within an engineering environment.

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What you'll do

You will be designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.

• Designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, including next-generation 3D-IC projects.
• Developing comprehensive test cases to ensure robust product functionality and performance.
• Collaborating with customers and internal engineering teams to resolve technical issues, including hands-on debugging and root cause analysis.
• Staying current with emerging trends, standards, and best practices in SLM and 3D-IC technologies.
• Contributing to the improvement of verification methodologies and automation flows.
• Documenting design specifications, verification plans, and results to ensure transparency and repeatability.
• Participating in code reviews and technical discussions to drive innovation and continuous improvement.

What you need

• BS/MS in Computer Science, Electrical Engineering, or related field.
• 8+ years of hands-on experience in RTL design and verification.
• Proficiency in EDA tools, Verilog, System Verilog, TCL scripting, and Formal Verification methodologies.
• Experience working in Unix/Linux environments.
• Strong debugging and problem-solving skills, especially in complex chip design environments.
• Excellent written and verbal communication skills in English.
• Knowledge of digital, analog, and mixed-signal IP/circuit design (a plus).
• Familiarity with 3D-IC standards and semiconductor verification best practices (desirable).

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What you'll do

You will be designing, developing, and maintaining StarRC, improving capacitance models and accuracy to enable new technologies ahead of the competition, developing next-generation parasitic extraction algorithms and flows to improve runtime, memory, and capacity, enhancing scripts and methodologies to analyze big data and optimize our products using advanced techniques like machine learning, collaborating with domain experts and the local R&D team to address complex technical challenges, contributing to the continuous improvement of our software development processes and tools.

What you need

• MS/PhD in Computer Science, Electrical Engineering, Physics, Mathematics, or a related field. Doctorate or equivalent industrial experience preferred.
• Solid C++ programming and debugging skills.
• Good knowledge of software development processes and tools, data structures, and algorithms.
• Experience in a Linux environment and familiarity with scripting languages.
• Understanding of numerical mathematics, machine learning, or AI as applied to optimization problems (nice to have).

Why this matters

• Advance the capabilities of StarRC, keeping it at the forefront of parasitic extraction technology.
• Enable new semiconductor technologies through improved modeling and accuracy.
• Enhance the performance and efficiency of our tools, benefiting customers in the semiconductor industry.
• Drive innovation by integrating machine learning techniques into our product development.
• Support the development of cutting-edge technologies that shape the future of electronics.
• Contribute to the success of Synopsys by delivering high-quality, reliable software solutions.

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