As a Senior Manager, ASIC Digital Design, you will lead a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions. You will collaborate with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.

Key responsibilities include:

• Leading a diverse team of design engineers in the development of next-generation SERDES PHY IP solutions
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products
• Planning, scheduling, and driving all phases of SERDES PHY IP design, from specification through productization and customer support
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles
• Mentoring and developing team members, fostering technical growth, and a culture of innovation
• Engaging customers, providing support for successful IP integration into their SoCs, and addressing technical challenges

The impact you will have includes delivering industry-leading SERDES PHY IP solutions that set new benchmarks for speed, bandwidth, and efficiency, empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications, and driving technical innovation that strengthens Synopsys' leadership in the mixed-signal IP market.

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Job Description

We are seeking a visionary technical leader with a great passion for innovation in semiconductor design. With a foundation in electrical engineering and a track record of managing high-performing design teams, you excel in guiding complex digital projects from concept to commercialization. Your expertise spans synthesizable Verilog and SystemVerilog, and you’re adept at navigating the intricacies of front-end flows, including linting, synthesis, static timing analysis, and power optimization. You thrive in collaborative environments, working seamlessly with cross-functional teams - architecture, verification, physical implementation, and firmware - to deliver industry-leading SecurityIP solutions.

Responsibilities

• Leading a diverse team of design engineers in the development of next-generation SecurityIP solutions.
• Collaborating with architects, verification, physical implementation, and firmware teams to deliver comprehensive IP products.
• Driving all phases of SecurityIP design, from specification through productization and customer support.
• Ensuring project success by achieving optimal timing, performance, and power goals across multiple design cycles.
• Mentoring and developing team members, fostering technical growth and a culture of innovation.
• Engaging with customers, providing support for successful IP integration into their SoCs, and addressing technical challenges.

Impact

• Delivering industry-leading SecurityIP solutions that set new benchmarks for speed, bandwidth, and efficiency.
• Empowering semiconductor customers to build high-performance, low-power chips for cutting-edge applications.
• Driving technical innovation that strengthens Synopsys’ leadership in the mixed-signal IP market.
• Mentoring and growing a world-class engineering team, ensuring continued excellence and market relevance.
• Enhancing product quality and reliability through rigorous design and verification processes.
• Facilitating successful customer adoption and satisfaction through expert support and problem-solving.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, with 12-15 years of complex technical development experience.
• Minimum 2 years’ experience in people management and employee development.
• Proficiency in synthesizable Verilog and SystemVerilog design concepts and implementation.
• Strong background in front-end design flows: linting, synthesis, static timing analysis (STA), cross-domain clocking, DFT, and power optimization.
• Excellent communication skills and the ability to work independently and collaboratively.
• Understanding of SecurityIP architecture is a plus.

Team

You’ll join the Synopsys SecurityIP team - a global, diverse group at the forefront of silicon IP innovation. Our team develops both digital and analog components, creating high-performance, high-bandwidth, low-latency, and low-power solutions for the world’s most advanced semiconductor technologies. We collaborate across engineering disciplines to deliver market-leading products and drive Synopsys’ leadership in chip design.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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As an infrastructure engineer at Cursor, you will be responsible for building highly-available distributed systems, dealing with the woes of scaling to millions of programmers, and working with various databases, proxies, caches, task queues, and orchestration systems. You will also be involved in shipping infra for safely computing import graphs and shadow lints.

Some sample projects you may work on include creating a retrieval system that processes 10,000,000,000+ files, staring at esoteric flame graphs to performance engineer our reranking library, and working with many databases, proxies, caches, task queues, and orchestration systems.

We're a team that enjoys spirited debate, crazy ideas, and shipping code. We're looking for people who are truth-seeking, passionate, and creative, and who are comfortable working in a flat organisational structure.

Our offices are located in North Beach, San Francisco and Manhattan, New York, and are replete with well-stocked libraries. We're an in-person team, and we enjoy working together to build something amazing.

If you're passionate about building highly-available distributed systems, and you're looking for a challenging and rewarding role, we'd love to hear from you.

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Frontend Engineer, Identity

Location

San Francisco

Employment Type

Full time

Location Type

On-site

Department

Applied AI

Compensation

• $230K – $325K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team

The Applied team at OpenAI brings cutting-edge AI technology into the hands of millions of people and businesses worldwide. We build and operate products such as ChatGPT, Sora, and the OpenAI API, delivering state-of-the-art multimodal capabilities across text, image, audio, and video. Our work spans product engineering, large-scale inference, and platform infrastructure — all designed to safely and reliably support global usage.

About the Role

As a Frontend Engineer on OpenAI’s Identity team, you’ll build the user-facing experiences that make secure access to OpenAI simple, clear, and trustworthy for organizations. You’ll design and implement core identity flows — such as sign-in, account management, permissions, and admin experiences — that enable enterprises to adopt OpenAI’s products with confidence.

You’ll work closely with design, product, security, and backend teams to translate complex identity systems like SSO, RBAC, and identity federation into intuitive, reliable interfaces. Your work will directly shape how users and administrators understand and manage access across OpenAI’s products, helping unlock secure, large-scale enterprise adoption of AI.

This role is based in San Francisco, California. There may be relocation options available.

In this role, you will:

• Build scalable, reusable frontend components and patterns for core identity experiences, including sign-in flows, account management, permissions, and admin surfaces.

• Partner closely with backend and security engineers to deliver end-to-end identity capabilities such as SSO, RBAC, SCIM provisioning, and delegated access through clear, intuitive interfaces.

• Translate complex authentication and authorization systems (e.g., SAML, OIDC, OAuth) into user experiences that are understandable, reliable, and trustworthy for both admins and end users.

• Help define frontend architecture, standards, and patterns for a shared identity platform used across OpenAI’s products.

• Build internal tools and surfaces that enable teams across OpenAI to integrate, manage, and reason about identity and access control effectively.

• Collaborate with Product, Design, Security, and Go-To-Market partners to turn ambiguous enterprise requirements into high-quality, user-centered interfaces.

You might thrive here if you:

• Have at least 5+ years of frontend engineering experience building and maintaining production-grade web applications, with a focus on usability, scalability, and long-term maintainability.

• Bring deep frontend expertise and genuine enthusiasm for frontend frameworks, performance optimization, latency, and building reusable, composable UI systems.

• Are excited to take ownership of critical access flows, helping scale and improve sign-in, permissions, and account experiences across OpenAI’s products.

• Enjoy working closely with cross-functional partners — including product, design, security, and go-to-market teams — to shape thoughtful, user-centered solutions.

• Have experience evolving or re-architecting production systems to support new capabilities and increased scale.

• Care deeply about user experience and take pride in crafting interfaces that make complex identity and access systems feel simple and trustworthy.

• Thrive in fast-moving environments where re

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What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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