What you'll do

You will be responsible for designing and developing cutting-edge semiconductor solutions, including chip architecture, circuit design, and verification. You will work on intricate tasks such as debugs and development of complex digital blocks within next-generation SERDES architectures.

• Run Spyglass CDC/RDC/Lint and Tmax for code quality, clock domain crossing, and reset domain crossing checks.
• Develop and optimize synthesis constraints to ensure robust and high-performance ASIC implementations.

What you need

• B.E/B.Tech/M.Tech in Electronics & Communication Engineering, Electrical Engineering, or related field.
• 3-8 years of hands-on experience in ASIC digital design, with a strong foundation in HDL coding (Verilog).
• Proficiency in synthesis constraints and basics of Static Timing Analysis (STA).
• Experience with linting and verification tools such as Spyglass CDC/RDC/Lint and Tmax.
• Working knowledge of scripting languages like Perl, Shell, Python, or TCL for design automation.
• Familiarity with high-speed SERDES protocols and RTL implementation is a strong advantage.

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