These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.

You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.

Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.

Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.

Key Responsibilities:

• Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

• Hands-on execution of layout development, ensuring precision and adherence to industry standards.

• Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.

• Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.

• Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.

Requirements:

• BTech/MTech degree in Electrical Engineering, Electronics, or related field.

• 5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).

• Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.

• Strong understanding of floorplan techniques and deep submicron effects.

• Proven ability to lead projects and deliver best product quality within tight timelines.

Preferred Qualifications:

• Collaborative and team-oriented, with a commitment to inclusion and diversity.

• Detail-oriented, with strong problem-solving and analytical skills.

• Effective communicator, both written and verbal, with excellent interpersonal abilities.

• Adaptable and eager to learn, embracing new technologies and methodologies.

• Empathetic mentor, fostering accountability, ownership, and technical growth in others.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.

• In addition to company holidays, we have ETO and FTO Programs.

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Save for your future with our retirement plans that vary by region and country.

• Competitive salaries.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.

You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.

You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.

You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.

Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.

If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.

Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.

Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.

Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.

Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.

Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.

Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.

Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.

Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.

Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.

Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.

Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.

Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.

Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.

Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.

Shaping the future of chip design and verification technologies through your expertise and leadership.

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