This is a product engineering role first and foremost. You'll work closely with designers and product managers to bring features from concept to shipped experience, obsessing over the details that make the difference: how something feels when you first land on it, how smoothly a new interaction flows, how an interface holds up under real-world use.

The pace is fast, the product is evolving quickly, and the opportunity to have a visible, direct impact on how millions of people use AI is real. If you love building consumer products and care about getting the details right, this could be a great fit.

Responsibilities:

• Build and ship user-facing features for claude.ai's web experience, working closely with designers to bring detailed, polished interactions to life

• Translate design intent into high-quality implementations , paying close attention to accessibility and the small details that add up to a great product feel

• Build responsive applications that work well across devices and screen sizes, and actively care about the performance characteristics that shape how the product feels to use , latency, responsiveness, and reliability are first-class concerns, not afterthoughts

• Collaborate tightly with product managers to understand user needs, shape feature scope, and make informed tradeoffs as you build

• Iterate quickly based on user feedback and internal testing, improving the experience on a continuous basis

• Work with the UI Platform team to consume shared components and tooling effectively, and flag gaps or pain points that would help the broader team move faster

• Help maintain a high bar for code quality and consistency within the consumer product codebase

You may be a good fit if you:

• Have 5+ years of experience building consumer-facing web products, with a strong emphasis on UI quality and user experience

• Are proficient in React, Next.js, and TypeScript, and have experience with Node.js on the backend side of the stack

• Genuinely care about the user experience , not just how something looks, but how fast it loads, how reliably it works, and how it feels across devices. You think about latency and responsiveness the same way you think about design

• Collaborate well with designers and product managers, and enjoy the iterative process of turning a design into something that works beautifully in the browser

• Are comfortable working in a fast-moving environment where priorities shift and shipping quickly matters

• Pick up slack, even if it goes outside your job description

Strong candidates may also have experience with:

• Accessibility best practices and building inclusive user interfaces

• Performance optimization for consumer web apps , profiling, reducing bundle size, improving rendering performance, and understanding where latency comes from end-to-end

• Designing and implementing responsive layouts that work well across screen sizes and devices

• Working on products with real-time or streaming interactions (chat interfaces, live updates, etc.)

• User research or usability testing, or a track record of incorporating user feedback into product decisions

• Working on AI/ML products or in fast-moving consumer product environments

Candidates need not have:

• 100% of the skills needed to perform the job

• Formal certifications or education credentials

Annual compensation range for this role is $320,000-$405,000 USD.

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The ideal candidate will have 5+ years of experience in electrical engineering, focusing on system-level design, development, and testing. They will also have a degree in Electrical Engineering or equivalent and experience with analog and digital electronics design, testing, and troubleshooting. Proficiency in laboratory skills, including setting up and running experiments, is also required.

The Electrical Engineer will participate in system testing at laboratory, ground, and flight test levels, providing detailed data analysis and feedback. They will conduct troubleshooting and testing of electronic components and subsystems to ensure optimal performance. The successful candidate will work closely with technical leads and project teams to support system integration efforts.

The Electrical Engineer will document test results, system designs, and processes to maintain thorough technical records. They will also assist in the design and development of PCB layouts in collaboration with the electrical engineering team.

The salary range for this role is $129,000-$171,000 USD. The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full-time offers; and are considered part of Anduril's total compensation package.

Additionally, Anduril offers top-tier benefits for full-time employees, including healthcare benefits, income protection, generous time off, family planning and parenting support, mental health resources, professional development, commuter benefits, relocation assistance, and a retirement savings plan.

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Core Responsibilities: Define block-based build strategies explicitly compatible with facility geometry and crane systems Establish block size, weight, and envelope targets that optimize throughput and flow Translate vessel class, annual build rate, and steel tonnage into facility capacity requirements Define pre-outfitting rules that maximize upstream labor and minimize shipboard work Identify and eliminate facility-driven throughput bottlenecks early in design Ensure material flow supports parallel workstreams and predictable sequencing Integrate build strategy across facilities, heavy lift, manufacturing engineering, and design teams

Required Experience & Skills: Experience in block-based ship construction or heavy modular fabrication environments Strong understanding of crane-driven production systems and facility constraints Demonstrated throughput and production-flow mindset Ability to work early with incomplete information to shape irreversible facility decisions Comfort operating at the interface of design, facilities, and operations

Preferred Background: Experience influencing shipyard layouts, crane strategies, or major facility decisions Background in shipbuilding and facility layout design Experience in 3D modeling work flows

Benefits: Medical Insurance: Comprehensive health insurance plans covering a range of services Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care Saronic pays 100% of the premium for employees and 80% for dependents Time Off: Generous PTO and Holidays Parental Leave: Paid maternity and paternity leave to support new parents Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses Retirement Plan: 401(k) plan Stock Options: Equity options to give employees a stake in the company’s success Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

Additional Information: This role requires access to export-controlled information or items that require “U.S. Person” status.

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You will collaborate cross-functionally with other electrical, firmware/software, mechanical, and manufacturing/quality teams to design, validate, and deliver robust electronic solutions.

Key Responsibilities:

• Primarily digital and power-based designs, but analog design is a possibility.
• Own the entire PCB design lifecycle, including requirements, major component selection, block diagrams, schematic, circuit analysis, placement, routing, DFA/DFM review, prototype testing, and documentation.
• Create and maintain BOMs, design files, netlists, and manufacturing documentation.
• Work closely with mechanical engineers to integrate PCBs into enclosures and assemblies.
• Lead or support prototype bring-up, debugging, and testing with support from the firmware/software teams (Capability to write firmware/software for bring-up is a plus).
• Perform signal integrity, power budgeting, and thermal analysis as needed.
• Review and optimize designs for EMC/EMI compliance and environmental robustness.
• Interface with fabrication and assembly vendors, addressing build issues and driving quality improvements.
• Participate and cross-collaborate in design reviews and peer reviews to ensure high standards.
• Contribute to and improve engineering processes, libraries, and design guidelines.
• Support ITAR/export compliance and follow relevant standards such as MIL-STD’s, IPC-610/6012, etc.

Required Qualifications:

• Bachelor’s degree in Electrical Engineering or related field.
• 3+ years of professional experience in PCB schematic and layout design.
• Proficiency with Altium Designer (or other equivalent EDA tools).
• Experience with multi-layer board design and high-speed or mixed-signal circuitry.
• Strong understanding of electronic components, circuit theory, and board-level design principles.
• Ability to interpret datasheets, standards, and mechanical constraints.
• Proven experience with design for manufacturing (DFM) and design for test (DFT).

Preferred Qualifications:

• Experience in defense, aerospace, or other safety/mission-critical industries.
• Familiarity with ruggedized systems, high-temperature settings, water-intrusion protection, and other environmental requirements.
• Knowledge of MIL-STD, IPC standards, or similar frameworks.
• Experience with SPICE simulations, Signal Integrity Analysis, or reliability engineering.
• Ability to work with firmware, FPGA, or embedded teams.
• Active or previous security clearance (or ability to obtain one).
• Ownership mentality and attention to detail.
• Ability to work both independently and in multidisciplinary teams.
• Strong organizational and time management skills.
• Comfortable working in a fast-paced, product-focused environment.

Benefits:

• Medical Insurance: Comprehensive health insurance plans covering a range of services
• Dental and Vision Insurance: Coverage for routine dental check-ups, orthodontics, and vision care
• Saronic pays 100% of the premium for employees and 80% for dependents
• Time Off: Generous PTO and Holidays
• Parental Leave: Paid maternity and paternity leave to support new parents
• Competitive Salary: Industry-standard salaries with opportunities for performance-based bonuses
• Retirement Plan: 401(k) plan
• Stock Options: Equity options to give employees a stake in the company’s success
• Life and Disability Insurance: Basic life insurance and short- and long-term disability coverage
• Additional Perks: Free lunch benefit and unlimited free drinks and snacks in the office

Physical Demands:

• Prolonged periods of sitting at a desk and working on a computer.
• Occasional standing and walking within the office.
• Manual dexterity to operate a computer keyboard, mouse, and other office equipment.
• Visual acuity to read screens, documents, and reports.
• Occasional reaching, bending, or stooping to access file drawers, cabinets, or office supplies.
• Lifting and carrying items up to 20 pounds occasionally (e.g., office supplies, packages).

Additional Information:

This role requires access to export-controlled information or items that require “U.S. Person” status. As defined by U.S. law, individuals who are any one of the following are considered to be a “U.S. Person”: (1) U.S. citizens, (2) legal permanent residents (a.k.a. green card holders), and (3) certain protected classes of asylees and refugees, as defined in 8 U.S.C. 1324b(a)(3).

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As a Sr. Manager of R&D Engineering, you will lead a team of engineers in developing cutting-edge CMOS embedded memory technologies. You will be responsible for designing architecture and circuit implementation for ultra-high-speed, ultra-low-power, or high-density designs. You will also perform schematic entry, circuit simulation, layout planning, and supervision, as well as verify and validate designs to ensure high quality and performance.

The ideal candidate will have a strong background in memory compiler development, with a minimum of 8-10 years of experience in CMOS memory design, circuit simulation, and memory layout design. You will also have experience with layout parasitic extraction and verification tools, as well as programming skills in C-Shell, Perl, C++, or JavaScript.

As a leader, you will be responsible for mentoring and guiding a team of engineers, enhancing workflows and methodologies, and driving project success. You will also be expected to communicate effectively with cross-functional teams, including CAD and Frontend engineers, to automate memory compilers and generate EDA models.

At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.

You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.

Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.

Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.

Key Responsibilities:

• Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.

• Hands-on execution of layout development, ensuring precision and adherence to industry standards.

• Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.

• Estimating project efforts, planning schedules, and executing projects in cross-functional settings.

• Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.

• Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.

Requirements:

• BTech/MTech degree in Electrical Engineering, Electronics, or related field.

• 5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).

• Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.

• Strong understanding of floorplan techniques and deep submicron effects.

• Proven ability to lead projects and deliver best product quality within tight timelines.

Preferred Qualifications:

• Collaborative and team-oriented, with a commitment to inclusion and diversity.

• Detail-oriented, with strong problem-solving and analytical skills.

• Effective communicator, both written and verbal, with excellent interpersonal abilities.

• Adaptable and eager to learn, embracing new technologies and methodologies.

• Empathetic mentor, fostering accountability, ownership, and technical growth in others.

Benefits:

• Comprehensive medical and healthcare plans that work for you and your family.

• In addition to company holidays, we have ETO and FTO Programs.

• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• Save for your future with our retirement plans that vary by region and country.

• Competitive salaries.

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As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.

Key responsibilities include:

• Proposing and developing advanced layout design techniques and methodologies
• Running verification on existing designs to assess PDK update impacts
• Creating innovative scripts to minimize rework
• Collaborating with multiple organizations and teams across global time zones

The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.

This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Collaborating with local and international teams to develop layouts for complex analog and mixed-signal designs in advanced technology nodes (3nm, 2nm, and beyond).

Utilizing Synopsys suite of tools and full custom analog layout design tools (e.g., Custom Compiler) to create and optimize circuit layouts.

Implementing and verifying designs using industry-leading verification tools such as ICV, Calibre and Star-RCXT...

Developing SERDES sub-circuit layouts (RX, TX, PLL, etc.) and optimizing for signal integrity, including clock/data routes, differential routing, and shielding.

Applying scripting techniques (TCL, Python, etc.) to automate layout processes and improve workflow efficiency.

Ensuring designs meet ESD constraints, mitigate latch-up risks, and optimize for reliability issues such as EM and IR drop.

Designing custom digital logic cell layouts and associated logic path routing for mixed-signal integration.

Refining layouts to minimize parasitic effects and enhance matching, reliability, and performance.

Delivering high-quality IP that powers next-generation semiconductor products for global customers.

Enabling Synopsys to maintain leadership in advanced technology node design and IP development.

Contributing to the creation of reliable, high-performance silicon chips used in communications.

Driving innovation in analog and mixed-signal layout methodologies and tools.

Enhancing cross-team collaboration and knowledge sharing to accelerate project timelines and improve outcomes.

Ensuring robust design practices that minimize risk and maximize reliability, meeting stringent industry standards.

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Your Contribution:

• Enhance selected concepts through rigorous UI/UX verification.
• Conduct targeted research to support interface and interaction solutions.
• Develop experience-focused design proposals and functional prototypes.
• Visualize development results using professional graphic and video formats.
• Manage prototyping resources and recruit participants for concept validation.
• Support Innovation Program activities and workshops.

Key Qualifications:

• Proficiency in UI design and digital/physical prototyping tools (e.g., Figma, GitHub, Adobe XD, or rapid hardware prototyping).
• Strong visualization skills in layout design, motion graphics, and video editing.
• Mastery of Design Thinking: from user research to iterative prototyping.
• Fluent English for articulating design logic and presenting results.

Why Join Us?

• Hands-on experience: Work on meaningful projects that impact Logitech’s innovative products.
• Mentorship: Learn from experienced team members and leaders in the industry.
• Global exposure: Collaborate with teams across different regions and time zones.
• Innovation-driven culture: Contribute to a team that values creativity, curiosity, and user-focused design.

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What you'll do

• Designing and integrating memory leafcells and standard cell layouts.
• Optimizing layouts for speed, area, and power.
• Running and debugging DRC, LVS, and ERC checks.
• Collaborating with circuit and verification engineers.

What you need

• 2+ years in custom, standard cell, or memory layout design.
• Experience with FinFET, DRC, LVS, ERC, and boundary conditions.
• Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).

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What you'll do

Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies.

• Reviewing and analyzing floorplans and intricate circuits with circuit designers.

• Running complete sets of design verification tools available on AMS blocks.

• Working with the circuit design team to plan/schedule work and coordinate vital layout tradeoffs as needed.

• Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.

• Exceeding engineering specifications and expectations by working closely with the circuit design team.

What you need

• B.Tech/M.Tech with 5+ years of relevant experience.

• Proven experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.

• Experience in implementing analog layouts to achieve tight matching, low noise, and low power consumption.

• High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.

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What you'll do

• Lead the physical layout design of advanced memory IP (SRAM, ROM, eDRAM, etc.) at cell, array, and peripheral levels
• Ensure compliance with foundry process design rules (DRC/LVS) and memory-specific constraints

What you need

• Bachelor's or Master's degree in Electronics Engineering, Telecommunication, Physics, or related fields
• Minimum of 5 years of experience in layout design

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What you'll do

Reviewing SERDES standards to develop innovative transceiver architectures and sub-block specifications for Multi-Gbps NRZ & PAM4 SERDES IP.

• Investigating and architecting advanced circuit solutions to overcome bottlenecks, achieving breakthroughs in power efficiency, area reduction, and performance.

What you need

• Collaborating with cross-functional teams including analog, digital, and layout engineers.

Why this matters

As a trusted leader in the analog design community, your attention to detail, ownership mindset, and commitment to quality position you for success.

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