{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/layout-design"},"x-facet":{"type":"skill","slug":"layout-design","display":"Layout Design","count":27},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f7487da0-3dc"},"title":"Sr. Electrical System Validation Engineer","description":"<p>We made history and now we work to transform the future – for our customers, our communities and our families. You&#39;ll see your work on the road every day, helping people move freely and pursue their dreams. At Ford, you can build more than vehicles. Come build what matters.</p>\n<p>Ford&#39;s Electric Vehicles, Digital and Design (EVDD) team is charged with delivering the company’s vision of a fully electric transportation future. EVDD is customer-obsessed, entrepreneurial, and data-driven and is dedicated to delivering industry-leading customer experience for electric vehicle buyers and owners. You’ll join an agile team of doers pioneering our EV future by working collaboratively, staying focused on only what matters, and delivering excellence day in and day out. Join us to make positive change by helping build a better world where every person is free to move and pursue their dreams.</p>\n<p>In this position... The Sr. Electrical System Validation Engineer will contribute to the validation of the Low Voltage systems and be responsible for ensuring its reliable performance. You will lead system-level design and validation activities and work side by side with various cross-functional teams to support product design, vehicle behaviors definition, prototype bring-up, and validation with a system level focus. You will lead bring-up and validation activities for each vehicle build and be responsible for overall functionality and performance of Low Voltage systems throughout product life cycle. You will conceptualize, design, engineer, develop, and support the launch of next-generation vehicle platform architectures for electric vehicles.</p>\n<p><strong>Responsibilities</strong></p>\n<p><strong>What you&#39;ll do...</strong></p>\n<ul>\n<li>Perform bench level and vehicle level electrical system testing and validation</li>\n<li>Perform Worst Case Circuit Analysis on power electronics converters and electrical systems</li>\n<li>Review schematics and layouts for Low voltage ECUs, body controllers, and zonal modules</li>\n<li>Propose electrical circuit/system design changes to improve electrical system performance</li>\n<li>Perform electrical system fault testing and validate system protection strategies</li>\n<li>Electrical system power budget testing and validation</li>\n<li>Electrical system simulation to characterize low voltage system stability</li>\n<li>Develop proper test plans to validate system performance in low voltage electrical systems</li>\n<li>Gain deep technical knowledge on existing low voltage system architecture and propose strategies to enhance system reliability and stability</li>\n<li>Work with component suppliers to characterize the loads in a low voltage system</li>\n<li>Determine safe operating voltage range and other relevant constraints for electrical system loads</li>\n<li>Play an active role in low voltage system failure root cause analysis</li>\n<li>Support low voltage system requirement definition</li>\n<li>Ensure reliability of low voltage system by proposing proper load management strategies</li>\n<li>Perform trade studies to realize efficient system design strategies and optimize for cost</li>\n</ul>\n<p><strong>Qualifications</strong></p>\n<p><strong>You&#39;ll have...</strong></p>\n<ul>\n<li>B.S in Electrical, or Computer Engineering, or equivalent combination of relevant education and experience</li>\n<li>8+ years of combined electrical HW design and low voltage system validation experience</li>\n<li>3+ years of experience with performing WCCA analysis</li>\n<li>Power Electronics HW development experience including schematic and layout design, board bring up, and bench testing</li>\n<li>Deep technical knowledge on power converter topologies including isolated and non-isolated</li>\n<li>Extensive hands-on experience in power electronics and electrical system testing</li>\n<li>Experience and working knowledge of systems development and electric vehicle’s electrical architecture</li>\n<li>Strong understanding of electrical engineering fundamentals and ability to apply them to automotive concepts</li>\n<li>Proven debugging and diagnostic skills in electrical, mechanical, and software domains</li>\n<li>Experience with designing test plans to validate automotive low voltage systems</li>\n<li>Strong written and verbal communication skills</li>\n<li>An eagerness to work cross-functionally in a dynamic environment where you are part of a high performing team</li>\n<li>A systems approach to design and development with the desire and curiosity to strive for exceptional delivery execution and continuous improvement</li>\n</ul>\n<p><strong>Even better, you may have...</strong></p>\n<ul>\n<li>Master’s degree in electrical engineering, Computer Science, or related fields</li>\n<li>10+ years of combined electrical HW design and low voltage system validation experience</li>\n<li>5+ years of WCCA experience</li>\n<li>Strong knowledge of power electronics system design</li>\n<li>Experienced with advanced problem-solving tools such as fish-bone diagram, Design For Six Sigma (DFSS), FA report, 8D documentation, etc.</li>\n<li>Having semiconductor level knowledge is a big plus</li>\n</ul>\n<p><strong>Benefits</strong></p>\n<p>At Ford Motor Company, we offer a comprehensive benefits package that includes:</p>\n<ul>\n<li>Immediate medical, dental, vision and prescription drug coverage</li>\n<li>Flexible family care days, paid parental leave, new parent ramp-up programs, subsidized back-up child care and more</li>\n<li>Family building benefits including adoption and surrogacy expense reimbursement, fertility treatments, and more</li>\n<li>Vehicle discount program for employees and family members and management leases</li>\n<li>Tuition assistance</li>\n<li>Established and active employee resource groups</li>\n<li>Paid time off for individual and team community service</li>\n<li>A generous schedule of paid holidays, including the week between Christmas and New Year’s Day</li>\n<li>Paid time off and the option to purchase additional vacation time</li>\n</ul>\n<p><strong>Salary</strong></p>\n<p>This position is a salary grade 8 and ranges from $115,000-$192,900. Final determination of salary grade will be based on candidate&#39;s skills and experience, and base salary will be set within the applicable range according to job scope, responsibility and competitive market value.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f7487da0-3dc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Ford Motor Company","sameAs":"https://www.ford.com/","logo":"https://logos.yubhub.co/ford.com.png"},"x-apply-url":"https://efds.fa.em5.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/job/61910","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$115,000-$192,900","x-skills-required":["B.S in Electrical, or Computer Engineering, or equivalent combination of relevant education and experience","8+ years of combined electrical HW design and low voltage system validation experience","3+ years of experience with performing WCCA analysis","Power Electronics HW development experience including schematic and layout design, board bring up, and bench testing","Deep technical knowledge on power converter topologies including isolated and non-isolated","Extensive hands-on experience in power electronics and electrical system testing","Experience and working knowledge of systems development and electric vehicle’s electrical architecture","Strong understanding of electrical engineering fundamentals and ability to apply them to automotive concepts","Proven debugging and diagnostic skills in electrical, mechanical, and software domains","Experience with designing test plans to validate automotive low voltage systems","Strong written and verbal communication skills"],"x-skills-preferred":["Master’s degree in electrical engineering, Computer Science, or related fields","10+ years of combined electrical HW design and low voltage system validation experience","5+ years of WCCA experience","Strong knowledge of power electronics system design","Experienced with advanced problem-solving tools such as fish-bone diagram, Design For Six Sigma (DFSS), FA report, 8D documentation, etc.","Having semiconductor level knowledge is a big plus"],"datePosted":"2026-04-25T12:14:51.319Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Allen Park, MI"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Automotive","skills":"B.S in Electrical, or Computer Engineering, or equivalent combination of relevant education and experience, 8+ years of combined electrical HW design and low voltage system validation experience, 3+ years of experience with performing WCCA analysis, Power Electronics HW development experience including schematic and layout design, board bring up, and bench testing, Deep technical knowledge on power converter topologies including isolated and non-isolated, Extensive hands-on experience in power electronics and electrical system testing, Experience and working knowledge of systems development and electric vehicle’s electrical architecture, Strong understanding of electrical engineering fundamentals and ability to apply them to automotive concepts, Proven debugging and diagnostic skills in electrical, mechanical, and software domains, Experience with designing test plans to validate automotive low voltage systems, Strong written and verbal communication skills, Master’s degree in electrical engineering, Computer Science, or related fields, 10+ years of combined electrical HW design and low voltage system validation experience, 5+ years of WCCA experience, Strong knowledge of power electronics system design, Experienced with advanced problem-solving tools such as fish-bone diagram, Design For Six Sigma (DFSS), FA report, 8D documentation, etc., Having semiconductor level knowledge is a big plus","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":115000,"maxValue":192900,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_6a2541b3-e4a"},"title":"Senior Electrical Engineer, Space","description":"<p>This position involves working in a multi-disciplinary environment on the design, fabrication and flight testing of advanced payloads for Space. We are interested in candidates that are excited to work on new projects from conceptualization through production.</p>\n<p>As a Senior Electrical Engineer, you will work with the EE Manager and Systems Engineer to develop requirements, create block diagrams, make schematics, simulate circuit designs, perform layout or work with a layout engineer to design PCBs, generate drawings and documentation, perform design validation testing, support testing and test development, and debug support.</p>\n<p>We are looking for a team player with strong organization and communication skills, who has 8+ years of relevant experience, a B.S. in Electrical or Computer Engineering or equivalent, experience with schematic design, board bring-up, and power circuit design and implementation.</p>\n<p>Preferred qualifications include experience with schematic and layout design in Altium, performing PDN analysis, differential pair routing and debugging, and knowledge of common communication busses.</p>\n<p>US Salary Range: $146,000-$194,000 USD</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_6a2541b3-e4a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anduril","sameAs":"https://www.anduril.com/","logo":"https://logos.yubhub.co/anduril.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/andurilindustries/jobs/4871756007","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$146,000-$194,000 USD","x-skills-required":["schematic design","board bring-up","power circuit design and implementation","Altium","PDN analysis","differential pair routing and debugging","common communication busses"],"x-skills-preferred":["schematic and layout design in Altium","performing PDN analysis","knowledge of common communication busses"],"datePosted":"2026-04-24T15:19:40.942Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Costa Mesa, California, United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"schematic design, board bring-up, power circuit design and implementation, Altium, PDN analysis, differential pair routing and debugging, common communication busses, schematic and layout design in Altium, performing PDN analysis, knowledge of common communication busses","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":146000,"maxValue":194000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_187f60ea-7d2"},"title":"Analog Design, Engineer","description":"<p>We are open to hiring in GTA (Greater Toronto Area) and Ottawa. At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You possess a solid foundation in analog and mixed-signal circuit concepts, with hands-on experience using CAD tools for schematic entry and layout design. You approach challenges with a problem-solving mindset, leveraging your scripting abilities to automate workflows and enhance productivity. Your communication skills enable you to clearly document processes and share best practices, fostering a culture of knowledge exchange. You’re equally comfortable analyzing complex timing data and collaborating with senior engineers to improve design flows.</p>\n<p>Above all, you are motivated to make a tangible impact in the semiconductor industry. You seek opportunities to contribute to innovative projects, learn from experts, and grow your career in a supportive, technology-driven environment. If you are excited by the prospect of working on DDR and HBM memory IPs, and you enjoy taking initiative, you’ll find yourself at home in our team.</p>\n<p>\\* Simulating and analyzing the performance of analog and mixed-signal circuits for DDR and HBM memory PHY IP.</p>\n<p>\\* Characterizing circuit timing and validating timing .lib data against design specifications to ensure accuracy and reliability.</p>\n<p>\\* Collaborating with senior engineers across multiple disciplines to identify design flow bottlenecks and develop automation solutions.</p>\n<p>\\* Documenting workflows, design guidelines, and best practices to promote effective team collaboration and knowledge sharing.</p>\n<p>\\* Applying scripting languages (Python, TCL) to automate tasks and streamline design processes.</p>\n<p>The Impact You Will Have:</p>\n<p>\\* Enhancing the performance and reliability of industry-leading DDR and HBM memory PHY IP products.</p>\n<p>\\* Driving productivity improvements through workflow automation and innovative design solutions.</p>\n<p>\\* Facilitating knowledge sharing and documentation to strengthen team collaboration and project success.</p>\n<p>\\* Ensuring design compliance and accuracy through rigorous timing analysis and validation.</p>\n<p>\\* Supporting the evolution of Synopsys’ analog/mixed-signal design capabilities and methodologies.</p>\n<p>What You’ll Need:</p>\n<p>\\* BSc or MSc in Electrical Engineering, with relevant experience in analog/mixed-signal design.</p>\n<p>\\* Hands-on experience with schematic entry and layout design CAD tools.</p>\n<p>\\* Knowledge of timing liberty files and mixed-signal timing analysis.</p>\n<p>\\* Proficiency in scripting languages such as Python and TCL, with an ability to automate and optimize workflows.</p>\n<p>\\* Familiarity with AI prompt engineering and agentic AI concepts, integrating modern approaches into design processes.</p>\n<p>Who You Are:</p>\n<p>\\* Strong communicator, able to document and share technical information effectively.</p>\n<p>\\* Collaborative team player, eager to learn from and contribute to a diverse group of engineers.</p>\n<p>\\* Detail-oriented and organized, with excellent time management skills.</p>\n<p>\\* Proactive problem solver, comfortable tackling complex challenges in fast-paced environments.</p>\n<p>\\* Innovative thinker, continually seeking ways to improve processes and drive technological advancement.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will join a dynamic R&amp;D team focused on analog and mixed-signal design for DDR and HBM memory PHY IP products. Our team brings together engineers from various backgrounds, fostering an environment of collaboration, innovation, and continuous learning. We are committed to developing high-performance products that set industry standards, and we value the contributions and growth of each team member.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_187f60ea-7d2","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/markham/analog-design-engineer-16712/44408/94232569216","x-work-arrangement":"onsite","x-experience-level":null,"x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog and mixed-signal circuit concepts","CAD tools for schematic entry and layout design","scripting languages (Python, TCL)","timing liberty files and mixed-signal timing analysis","AI prompt engineering and agentic AI concepts"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:17:42.215Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Markham"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog and mixed-signal circuit concepts, CAD tools for schematic entry and layout design, scripting languages (Python, TCL), timing liberty files and mixed-signal timing analysis, AI prompt engineering and agentic AI concepts"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_2cb01a0d-088"},"title":"Custom Analog Enablement and Methodology, Staff Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate engineer with a deep understanding of custom analog layout design, eager to push boundaries and innovate in the semiconductor industry. You thrive in fast-paced environments and are energized by the opportunity to work with cutting-edge technology nodes, including sub-5nm FinFet and Gate-All-Around. With a strong foundation in electrical or computer engineering and over five years of hands-on experience, you possess advanced skills in scripting languages such as Tcl, Perl, and Python, enabling you to develop robust design methodologies and automation solutions. Your curiosity drives you to continually seek improvements in design processes, and you are adept at collaborating across global teams and time zones. You value clear communication, both in identifying technical challenges and presenting solutions, and you are known for your organizational skills and attention to detail. Your ability to debug LVS and DRC reports, coupled with basic knowledge of circuit design and digital synthesis workflows, positions you as a versatile contributor to any project. Above all, you are motivated by the chance to learn, grow, and make a meaningful impact in a supportive, innovative environment.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Proposing and developing advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python).</li>\n<li>Running verification on existing designs to assess PDK update impacts and creating innovative scripts to minimize rework.</li>\n<li>Collaborating with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.</li>\n<li>Working within a best-in-class IC design environment, utilizing industry-leading tools and custom in-house solutions.</li>\n<li>Driving the adoption of new layout methodologies by training and supporting global design teams.</li>\n<li>Maintaining and improving workflow automation, ensuring high productivity and quality in custom analog layout processes.</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Enhance efficiency and productivity of Synopsys IP design teams by enabling robust and scalable layout methodologies.</li>\n<li>Reduce design cycle times and rework through innovative scripting and workflow automation.</li>\n<li>Accelerate adoption of advanced technologies and nodes, keeping Synopsys at the forefront of semiconductor innovation.</li>\n<li>Foster cross-team collaboration, ensuring seamless integration of layout and design environments across global teams.</li>\n<li>Contribute to the development of industry-leading IP solutions, powering innovations in AI, automotive, IoT, and more.</li>\n<li>Drive continuous improvement and learning within the organization, sharing best practices and expertise with peers.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BS/MS in Electrical Engineering, Computer Engineering, or related field, with 4+ years of relevant experience.</li>\n<li>Expertise in custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes.</li>\n<li>Proficiency in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping.</li>\n<li>Ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.</li>\n<li>Basic understanding of circuit design and digital synthesis/place &amp; route workflows (ICC2/FC).</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You will join the Technology Enablement team, a global group of experts dedicated to advancing custom analog layout methodologies for Synopsys IP design. The team leverages industry-leading IC design tools and custom in-house solutions, working collaboratively to innovate and optimize workflows across the latest technology nodes. Supported by experienced software and CAD professionals, the team fosters a culture of continuous learning and growth, ensuring Synopsys remains a leader in semiconductor technology.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_2cb01a0d-088","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/custom-analog-enablement-and-methodology-staff-engineer-15233/44408/91711017792","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["custom analog layout design","sub-5nm FinFet/Gate-All-Around nodes","scripting languages: Tcl, Perl, and Python","LVS and DRC reports","circuit design and digital synthesis/place & route workflows"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:17:11.631Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"custom analog layout design, sub-5nm FinFet/Gate-All-Around nodes, scripting languages: Tcl, Perl, and Python, LVS and DRC reports, circuit design and digital synthesis/place & route workflows"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d0d01c2f-b91"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.</p>\n<p>Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.</p>\n<p>Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.</p>\n<p>Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.</p>\n<p>Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.</p>\n<p>Conducting design reviews and offering constructive feedback to enhance quality and performance.</p>\n<p>Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.</p>\n<p>Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.</p>\n<p>Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys&#39; IP products.</p>\n<p>Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.</p>\n<p>Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.</p>\n<p>Fostering collaboration across global teams, leading to improved methodologies and best practices.</p>\n<p>Maintaining the highest standards of quality, compliance, and performance in every design delivered.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d0d01c2f-b91","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/layout-design-sr-engineer/44408/93979726464","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["BTech/MTech in Electrical Engineering, Electronics, or related field","2+ years of relevant experience in IC layout design, preferably in standard cell libraries","Proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM)","Hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs","Strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:16:00.975Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"BTech/MTech in Electrical Engineering, Electronics, or related field, 2+ years of relevant experience in IC layout design, preferably in standard cell libraries, Proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), Hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, Strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c6b1618d-cd4"},"title":"Layout Design, Staff Engineer - High Speed Serdes","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>You are a passionate engineer with a keen eye for precision and detail, thriving in collaborative environments and excited by the challenge of delivering world-class layout designs for cutting-edge semiconductor products. With at least five years of hands-on experience in layout or mask design, you have a deep understanding of the nuances of IC layout and the ability to resolve complex issues with innovative solutions.</p>\n<p>Designing and developing complex layout structures for integrated circuits, ensuring compliance with design specifications and manufacturing requirements. Collaborating with cross-functional teams including circuit designers, verification engineers, and project managers to optimize layout solutions. Utilizing industry-standard EDA tools for layout creation, verification, and optimization. Performing physical verification (DRC, LVS) and resolving issues to ensure high-quality deliverables. Managing project timelines, resources, and deliverables, taking ownership of entire layout projects or processes. Mentoring junior engineers, providing guidance and sharing best practices to foster team growth and development. Participating in design reviews and contributing to process improvements and innovation within the team.</p>\n<p>Elevating the quality and reliability of Synopsys&#39; silicon solutions through meticulous layout design. Accelerating time-to-market for next-generation products by ensuring efficient and robust layout processes. Driving operational excellence by achieving and surpassing project goals within your area of responsibility. Enhancing collaboration across departments and with external partners, contributing to seamless integration of design and manufacturing workflows. Strengthening Synopsys&#39; reputation as a leader in semiconductor innovation through your expertise and attention to detail. Influencing the future of chip design by mentoring and empowering fellow engineers.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c6b1618d-cd4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/layout-design-staff-engineer-high-speed-serdes/44408/93673025568","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","mask design","IC layout","EDA tools","physical verification","project management","team leadership","design reviews","process improvement"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:37.279Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, mask design, IC layout, EDA tools, physical verification, project management, team leadership, design reviews, process improvement"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_9a65c18f-bd5"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR &amp; HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.</p>\n<p>Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.</p>\n<p>Accelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products. Ensuring robust and reliable IP performance through meticulous layout design and physical verification. Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more. Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader. Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements. Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization. Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally.</p>\n<p>BTech/MTech degree in Electronics, Electrical, or related engineering discipline. 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below). Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies. Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies. Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation. Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms. Ability to work independently and collaboratively, managing multiple tasks and priorities.</p>\n<p>Analytical thinker with strong problem-solving and debugging skills. Self-motivated, accountable, and results-driven. Collaborative team player who fosters trust and open communication. Adaptable and eager to learn new technologies and methodologies. Effective communicator with excellent interpersonal skills. Committed to diversity, inclusion, and continuous improvement.</p>\n<p>You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR &amp; HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_9a65c18f-bd5","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93917039696","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["IC layout design","CMOS, FinFET, and GAA process technologies","DRC, LVS, ERC, Antenna checks","Physical verification methodologies","Deep submicron effects, floorplan techniques, and layout matching","ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation","Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:14.206Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"IC layout design, CMOS, FinFET, and GAA process technologies, DRC, LVS, ERC, Antenna checks, Physical verification methodologies, Deep submicron effects, floorplan techniques, and layout matching, ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation, Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8fb79b22-cd0"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Designing and developing standard cell layouts</li>\n<li>Applying comprehensive sign-off checks</li>\n<li>Collaborating with global teams to resolve methodology issues and implement optimized layout designs</li>\n<li>Conducting design reviews and offering constructive feedback to enhance quality and performance</li>\n</ul>\n<p>You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization&#39;s goals.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8fb79b22-cd0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/layout-design-staff-engineer/44408/93979726448","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["IC layout design","standard cell libraries","Synopsys Custom Compiler","Virtuoso","Innovus/ICC2","ICV/Calibre","TSMC","Samsung","UMC","GlobalFoundries PDKs","Python","Tcl","Perl","SKILL","ICV","shell scripting"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:54.856Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"IC layout design, standard cell libraries, Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, ICV/Calibre, TSMC, Samsung, UMC, GlobalFoundries PDKs, Python, Tcl, Perl, SKILL, ICV, shell scripting"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_26310f57-d67"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong> You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills,both written and verbal,are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards.</li>\n<li>Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting.</li>\n<li>Mentoring and guiding junior engineers, fostering growth and technical excellence within the team.</li>\n<li>Estimating project efforts, planning schedules, and executing projects in cross-functional settings.</li>\n<li>Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes.</li>\n<li>Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate the integration of advanced silicon IP in SoCs, driving innovation in smart devices and systems.</li>\n<li>Enhance product differentiation and performance, enabling customers to meet demanding market requirements.</li>\n<li>Reduce time-to-market and risk for customers through robust layout design and technical leadership.</li>\n<li>Support Synopsys’ reputation as a leader in DDR &amp; HBM PHY IP development, contributing to industry benchmarks.</li>\n<li>Foster an inclusive and collaborative engineering culture that values accountability and technical excellence.</li>\n<li>Mentor and develop the next generation of layout engineers, ensuring sustained innovation and talent growth.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BTech/MTech in Electronics, Electrical Engineering, or related field.</li>\n<li>5+ years of relevant experience in layout design, preferably in DDR &amp; HBM PHY IP development.</li>\n<li>Deep understanding of submicron effects, floorplan techniques in CMOS, FinFET, GAA technologies (7nm and below).</li>\n<li>Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.</li>\n<li>Strong ability to lead projects, manage schedules, and ensure product quality within tight timelines.</li>\n<li>Excellent written, verbal communication, and interpersonal skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Innovative thinker with a proactive approach to problem-solving.</li>\n<li>Effective communicator and collaborator across diverse teams.</li>\n<li>Detail-oriented, accountable, and committed to high standards of quality.</li>\n<li>Mentor and leader, fostering growth and technical excellence.</li>\n<li>Adaptable, eager to learn, and open to new ideas and technologies.</li>\n<li>Champion for inclusion, diversity, and teamwork.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong> You will join a dynamic Silicon IP team focused on developing high-performance DDR and HBM PHY IPs. Our team values technical innovation, collaborative problem-solving, and continuous improvement. We work closely with cross-functional groups including design, verification, and customer support to deliver industry-leading solutions that shape the future of smart technology.</p>\n<p><strong>Rewards and Benefits:</strong> We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_26310f57-d67","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93917039712","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","DDR and HBM PHY IPs","CMOS, FinFET, and GAA technologies","floorplanning","layout matching","ESD, latch-up, PERC, EMIR, DFM","LEF generation","IO frame and pitch requirements"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:45.685Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, DDR and HBM PHY IPs, CMOS, FinFET, and GAA technologies, floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, IO frame and pitch requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1a49fd5b-a39"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills,both written and verbal,are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.</p>\n<p>Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards. Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting. Mentoring and guiding junior engineers, fostering growth and technical excellence within the team. Estimating project efforts, planning schedules, and executing projects in cross-functional settings. Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes. Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1a49fd5b-a39","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93917039728","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","DDR and HBM PHY IPs","CMOS, FinFET, and GAA at 7nm and below","floorplanning","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","IO frame requirements"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:45.472Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, DDR and HBM PHY IPs, CMOS, FinFET, and GAA at 7nm and below, floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, IO frame requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c33c02c5-da6"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR &amp; HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification. You thrive in dynamic environments, bringing a collaborative spirit and a growth mindset to every project. You value diversity and inclusion, recognizing the importance of varied perspectives in driving innovation. With a commitment to accountability, you consistently deliver quality results, demonstrating ownership and initiative in your work. Your communication skills,both verbal and written,enable you to effectively share ideas, provide feedback, and partner with cross-functional teams. You are motivated by the opportunity to work on cutting-edge technologies, always seeking to expand your knowledge and make a meaningful impact. Whether solving complex problems or optimizing layouts for performance, power, and area, you approach challenges with creativity and perseverance. You are ready to join Synopsys in shaping the future of silicon IP, contributing to products that empower customers to succeed in the Era of Smart Everything.</p>\n<p>Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c33c02c5-da6","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93942161072","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["IC layout design","Advanced process technologies","Deep submicron effects","Layout floorplanning","Physical verification","DRC","LVS","ERC","Antenna checks","ESD","Latch-up","EMIR","DFM","LEF generation"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:43.985Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"IC layout design, Advanced process technologies, Deep submicron effects, Layout floorplanning, Physical verification, DRC, LVS, ERC, Antenna checks, ESD, Latch-up, EMIR, DFM, LEF generation"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d4e4fda2-379"},"title":"Layout Design, Staff Engineer","description":"<p>As a Layout Design, Staff Engineer at Synopsys, you will design and develop standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will work on developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.</p>\n<p>Your responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.</p>\n<p>You will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.</p>\n<p>The impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys&#39; IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.</p>\n<p>To succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d4e4fda2-379","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/layout-design-staff-engineer/44408/93979726480","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Standard Cell Layout Design","Synopsys Custom Compiler","Virtuoso","Innovus/ICC2","ICV/Calibre","TSMC","Samsung","UMC","GlobalFoundries PDKs","Python","Tcl","Perl","SKILL","ICV","Shell Scripting","CMOS","DPT","EM/IR","ESD/latch-up","Noise","Digital Layout Fundamentals"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:39.515Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Standard Cell Layout Design, Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, ICV/Calibre, TSMC, Samsung, UMC, GlobalFoundries PDKs, Python, Tcl, Perl, SKILL, ICV, Shell Scripting, CMOS, DPT, EM/IR, ESD/latch-up, Noise, Digital Layout Fundamentals"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_848ce060-77e"},"title":"Layout Design, Sr Staff Engineer","description":"<p>You are a passionate, highly experienced layout design engineer who thrives at the intersection of technology leadership and hands-on technical execution. With a deep-rooted commitment to quality and innovation, you are adept at navigating the complexities of deep submicron CMOS, FinFET, and GAA process technologies. You possess a natural curiosity and drive to continuously learn, keeping yourself up to date with the latest industry advancements, particularly in advanced memory interface IP such as DDR and HBM.</p>\n<p>As a leader, you are motivated by mentoring and elevating your team, fostering a collaborative environment that encourages knowledge sharing and accountability. You are comfortable handling multi-faceted projects, from initial floorplanning to the final tape-out, and you have a proven ability to manage schedules, estimate efforts, and deliver best-in-class products on time.</p>\n<p>Your expertise spans across layout matching techniques, ESD protection, DFM, and advanced verification methodologies, enabling you to anticipate and solve complex challenges. You are recognised for your strong communication skills, both written and verbal, and you know how to clearly articulate technical concepts to cross-functional teams and customers alike.</p>\n<p>You are inclusive, collaborative, and open-minded, actively seeking diverse perspectives while fostering a supportive team culture. You are accountable and results-driven, with a demonstrated ability to take ownership and deliver on commitments.</p>\n<p>You will join a dynamic, high-impact team at the forefront of silicon IP innovation, dedicated to delivering world-class memory interface solutions. Our team thrives on technical excellence, close collaboration, and a shared commitment to pushing the boundaries of what&#39;s possible in chip design.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_848ce060-77e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-staff-engineer/44408/93942161024","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","CMOS","FinFET","GAA","DDR","HBM","ESD protection","DFM","advanced verification methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:10:43.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, CMOS, FinFET, GAA, DDR, HBM, ESD protection, DFM, advanced verification methodologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7181ae65-d2c"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a passionate and innovative Staff Engineer who thrives on turning complex technical challenges into industry-leading solutions. You will lead the design and development of next-generation DDR and HBM PHY IP layout, driving technical innovation and best practices. You will also provide technical mentorship and guidance to junior engineers, fostering skill development and knowledge sharing across the team.</p>\n<p>As a Staff Engineer, you will take ownership of layout planning, execution, and quality review processes to ensure on-time delivery of high-quality silicon IP. You will collaborate with cross-functional teams, including circuit design, verification, and product engineering, to meet project goals and customer requirements. You will also manage effort estimation, project scheduling, and execution in multi-disciplinary team settings.</p>\n<p>The successful candidate will have a strong command of deep submicron effects, advanced floorplan techniques, and process technologies such as CMOS, FinFET, and GAA. You will also have expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and bond-pad/IO frame design.</p>\n<p>If you are a proactive problem solver, ready to lead, mentor, and make a tangible impact in a dynamic, fast-paced environment, we encourage you to apply for this exciting opportunity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7181ae65-d2c","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93942161264","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical layout design","advanced process nodes","deep submicron effects","advanced floorplan techniques","process technologies","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad/IO frame design"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:10:05.687Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical layout design, advanced process nodes, deep submicron effects, advanced floorplan techniques, process technologies, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad/IO frame design"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8ec6d1f4-b98"},"title":"Layout Design, Staff Engineer","description":"<p>We are seeking a highly skilled Layout Design, Staff Engineer to join our team in Bengaluru. As a Staff Engineer, you will be responsible for leading the design and development of next-generation DDR and HBM PHY IP layout, driving technical innovation and best practices.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Lead the design and development of next-generation DDR and HBM PHY IP layout</li>\n<li>Provide technical mentorship and guidance to junior engineers</li>\n<li>Take ownership of layout planning, execution, and quality review processes</li>\n<li>Collaborate with cross-functional teams to meet project goals and customer requirements</li>\n<li>Manage effort estimation, project scheduling, and execution in multi-disciplinary team settings</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>BTech/MTech degree in Electronics, Electrical Engineering, or a related field</li>\n<li>Minimum 5 years of relevant experience in physical layout design, particularly in advanced nodes (7nm and below)</li>\n<li>Strong command of deep submicron effects, advanced floorplan techniques, and process technologies such as CMOS, FinFET, and GAA</li>\n<li>Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and bond-pad/IO frame design</li>\n<li>Demonstrated ability to lead projects, manage schedules, and deliver high-quality results within tight timelines</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li>Experience with industry-standard EDA tools for layout and verification</li>\n<li>Strong problem-solving skills and ability to work in a fast-paced environment</li>\n<li>Excellent communication and collaboration skills</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away from work programs</li>\n<li>Family support programs</li>\n<li>ESPP</li>\n</ul>\n<p>At Synopsys, we value diversity and inclusion and are committed to creating a workplace where everyone feels valued and supported. We are an equal opportunity employer and welcome applications from qualified candidates of all backgrounds.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8ec6d1f4-b98","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93942161216","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical layout design","deep submicron effects","advanced floorplan techniques","process technologies","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad/IO frame design"],"x-skills-preferred":["industry-standard EDA tools","problem-solving skills","communication skills","collaboration skills"],"datePosted":"2026-04-24T14:09:19.554Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical layout design, deep submicron effects, advanced floorplan techniques, process technologies, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad/IO frame design, industry-standard EDA tools, problem-solving skills, communication skills, collaboration skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d0dacac5-f8f"},"title":"Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR &amp; HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification.</p>\n<p>You will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.</p>\n<p>You will apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues. You will collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area.</p>\n<p>You will troubleshoot and debug layout challenges, continually improving methodologies and design outcomes. You will document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.</p>\n<p>Accelerating the integration of advanced silicon IP into customer SoCs, ensuring robust and reliable IP performance through meticulous layout design and physical verification, driving innovation in memory interface IPs, and reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d0dacac5-f8f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-engineer/44408/93942161152","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["IC layout design","advanced CMOS, FinFET, and GAA process technologies","deep submicron effects","layout floorplanning","physical verification","ESD, latch-up, EMIR, DFM, and LEF generation issues","layout matching techniques","Muhammad Ali","Cadence Virtuoso","Synopsys Custom Compiler"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:08:57.493Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"IC layout design, advanced CMOS, FinFET, and GAA process technologies, deep submicron effects, layout floorplanning, physical verification, ESD, latch-up, EMIR, DFM, and LEF generation issues, layout matching techniques, Muhammad Ali, Cadence Virtuoso, Synopsys Custom Compiler"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_700d5416-70b"},"title":"Visual Product Designer","description":"<p>You&#39;ll shape Gamma&#39;s visual identity within the product, collaborating with product, engineering, and design to ship stunning experiences across themes, layouts, and polish.</p>\n<p>As Visual Product Designer, you&#39;ll bring hands-on experience in presentation and graphic design to everything you ship. You&#39;ll demonstrate exceptional taste in color, type, layout, and hierarchy while balancing brand expression with usability. You&#39;ll create production-ready specs in Figma, ensuring every pixel serves both aesthetic and functional goals.</p>\n<p>Our team has a strong in-office culture and works in person 4–5 days per week in San Francisco. We love working together to stay creative and connected, with flexibility to work from home when focus matters most.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Own and evolve Gamma&#39;s visual system, bringing brand into the product in meaningful, delightful ways</li>\n<li>Collaborate with product, engineering, and design to ship visually polished experiences across themes, layouts, and end-to-end flows</li>\n<li>Apply exceptional visual craft and attention to detail across product surfaces</li>\n<li>Balance brand expression with usability at every touchpoint</li>\n<li>Create production-ready specs in Figma that guide engineering implementation</li>\n<li>Push the boundaries of what&#39;s possible with color, type, layout, and hierarchy in a digital product</li>\n</ul>\n<p><strong>What You&#39;ll Bring</strong></p>\n<ul>\n<li>4+ years in product or visual design, with a portfolio showcasing exceptional taste in color, type, layout, and hierarchy</li>\n<li>Demonstrated experience in presentation design and graphic design, with shipped work that balances brand expression and usability</li>\n<li>Proficiency in Figma and modern prototyping tools, with the ability to create production-ready specs</li>\n<li>Hands-on experience applying high-level visual craft and polish to digital products</li>\n<li>Experience building or evolving a design system&#39;s visual layer, and experience shipping presentation and storytelling tools at scale (Nice to have)</li>\n</ul>\n<p><strong>Compensation Range</strong></p>\n<p>The base salary for this full-time position, which spans multiple internal levels depending on qualifications, ranges between $140K - $250K plus benefits &amp; equity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_700d5416-70b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Gamma","sameAs":"https://gamma.com","logo":"https://logos.yubhub.co/gamma.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/gamma/3fe11347-22f8-4ca5-bbc7-11518f8ea802","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"Full time","x-salary-range":"The base salary for this full-time position, which spans multiple internal levels depending on qualifications, ranges between $140K - $250K plus benefits & equity.","x-skills-required":["Figma","prototyping tools","visual design","graphic design","color theory","type design","layout design","hierarchy design"],"x-skills-preferred":["design systems","presentation design","storytelling tools"],"datePosted":"2026-04-24T12:15:11.038Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Design","industry":"Technology","skills":"Figma, prototyping tools, visual design, graphic design, color theory, type design, layout design, hierarchy design, design systems, presentation design, storytelling tools","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":140000,"maxValue":250000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cee7bd81-c81"},"title":"UI Software Engineer, Claude.ai Consumer Product","description":"<p>We&#39;re looking for a talented engineer to join the team that builds the consumer web app , the interfaces, interactions, and moments that turn Claude from a capable model into a product people genuinely enjoy using.</p>\n<p>This is a product engineering role first and foremost. You&#39;ll work closely with designers and product managers to bring features from concept to shipped experience, obsessing over the details that make the difference: how something feels when you first land on it, how smoothly a new interaction flows, how an interface holds up under real-world use.</p>\n<p>The pace is fast, the product is evolving quickly, and the opportunity to have a visible, direct impact on how millions of people use AI is real. If you love building consumer products and care about getting the details right, this could be a great fit.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Build and ship user-facing features for claude.ai&#39;s web experience, working closely with designers to bring detailed, polished interactions to life</li>\n</ul>\n<ul>\n<li>Translate design intent into high-quality implementations , paying close attention to accessibility and the small details that add up to a great product feel</li>\n</ul>\n<ul>\n<li>Build responsive applications that work well across devices and screen sizes, and actively care about the performance characteristics that shape how the product feels to use , latency, responsiveness, and reliability are first-class concerns, not afterthoughts</li>\n</ul>\n<ul>\n<li>Collaborate tightly with product managers to understand user needs, shape feature scope, and make informed tradeoffs as you build</li>\n</ul>\n<ul>\n<li>Iterate quickly based on user feedback and internal testing, improving the experience on a continuous basis</li>\n</ul>\n<ul>\n<li>Work with the UI Platform team to consume shared components and tooling effectively, and flag gaps or pain points that would help the broader team move faster</li>\n</ul>\n<ul>\n<li>Help maintain a high bar for code quality and consistency within the consumer product codebase</li>\n</ul>\n<p>You may be a good fit if you:</p>\n<ul>\n<li>Have 5+ years of experience building consumer-facing web products, with a strong emphasis on UI quality and user experience</li>\n</ul>\n<ul>\n<li>Are proficient in React, Next.js, and TypeScript, and have experience with Node.js on the backend side of the stack</li>\n</ul>\n<ul>\n<li>Genuinely care about the user experience , not just how something looks, but how fast it loads, how reliably it works, and how it feels across devices. You think about latency and responsiveness the same way you think about design</li>\n</ul>\n<ul>\n<li>Collaborate well with designers and product managers, and enjoy the iterative process of turning a design into something that works beautifully in the browser</li>\n</ul>\n<ul>\n<li>Are comfortable working in a fast-moving environment where priorities shift and shipping quickly matters</li>\n</ul>\n<ul>\n<li>Pick up slack, even if it goes outside your job description</li>\n</ul>\n<p>Strong candidates may also have experience with:</p>\n<ul>\n<li>Accessibility best practices and building inclusive user interfaces</li>\n</ul>\n<ul>\n<li>Performance optimization for consumer web apps , profiling, reducing bundle size, improving rendering performance, and understanding where latency comes from end-to-end</li>\n</ul>\n<ul>\n<li>Designing and implementing responsive layouts that work well across screen sizes and devices</li>\n</ul>\n<ul>\n<li>Working on products with real-time or streaming interactions (chat interfaces, live updates, etc.)</li>\n</ul>\n<ul>\n<li>User research or usability testing, or a track record of incorporating user feedback into product decisions</li>\n</ul>\n<ul>\n<li>Working on AI/ML products or in fast-moving consumer product environments</li>\n</ul>\n<p>Candidates need not have:</p>\n<ul>\n<li>100% of the skills needed to perform the job</li>\n</ul>\n<ul>\n<li>Formal certifications or education credentials</li>\n</ul>\n<p>Annual compensation range for this role is $320,000-$405,000 USD.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cee7bd81-c81","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anthropic","sameAs":"https://www.anthropic.com/","logo":"https://logos.yubhub.co/anthropic.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/anthropic/jobs/5026097008","x-work-arrangement":"hybrid","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$320,000-$405,000 USD","x-skills-required":["React","Next.js","TypeScript","Node.js","Accessibility best practices","Performance optimization","Responsive layout design","Real-time or streaming interactions","User research or usability testing"],"x-skills-preferred":["AI/ML products","Fast-moving consumer product environments"],"datePosted":"2026-04-18T15:59:43.237Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco, CA | New York City, NY | Seattle, WA"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"React, Next.js, TypeScript, Node.js, Accessibility best practices, Performance optimization, Responsive layout design, Real-time or streaming interactions, User research or usability testing, AI/ML products, Fast-moving consumer product environments","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":320000,"maxValue":405000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_bef26761-dba"},"title":"Electrical Engineer","description":"<p>As an Electrical Engineer at Anduril Imaging, you will design and develop advanced electronics for airborne EO/IR systems, focusing on sensor electronics, aircraft interfaces, and power management. The successful candidate will contribute to the design, development, and testing of electronics for airborne EO/IR systems, including sensor electronics, aircraft interfaces, and power management. They will also support systems engineering teams in defining and refining requirements based on physics-based models of sensor and system performance.</p>\n<p>The ideal candidate will have 5+ years of experience in electrical engineering, focusing on system-level design, development, and testing. They will also have a degree in Electrical Engineering or equivalent and experience with analog and digital electronics design, testing, and troubleshooting. Proficiency in laboratory skills, including setting up and running experiments, is also required.</p>\n<p>The Electrical Engineer will participate in system testing at laboratory, ground, and flight test levels, providing detailed data analysis and feedback. They will conduct troubleshooting and testing of electronic components and subsystems to ensure optimal performance. The successful candidate will work closely with technical leads and project teams to support system integration efforts.</p>\n<p>The Electrical Engineer will document test results, system designs, and processes to maintain thorough technical records. They will also assist in the design and development of PCB layouts in collaboration with the electrical engineering team.</p>\n<p>The salary range for this role is $129,000-$171,000 USD. The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full-time offers; and are considered part of Anduril&#39;s total compensation package.</p>\n<p>Additionally, Anduril offers top-tier benefits for full-time employees, including healthcare benefits, income protection, generous time off, family planning and parenting support, mental health resources, professional development, commuter benefits, relocation assistance, and a retirement savings plan.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_bef26761-dba","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Anduril Imaging","sameAs":"https://www.anduril.com/","logo":"https://logos.yubhub.co/anduril.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/andurilindustries/jobs/5112749007","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$129,000-$171,000 USD","x-skills-required":["electrical engineering","system-level design","development","testing","analog electronics","digital electronics","laboratory skills","PCB layout design"],"x-skills-preferred":["sensor electronics","aircraft interfaces","power management","physics-based modeling","MATLAB","Python","C++"],"datePosted":"2026-04-18T15:57:02.181Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Lexington, Massachusetts, United States"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"electrical engineering, system-level design, development, testing, analog electronics, digital electronics, laboratory skills, PCB layout design, sensor electronics, aircraft interfaces, power management, physics-based modeling, MATLAB, Python, C++","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":129000,"maxValue":171000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e76957dd-344"},"title":"R&D Engineering, Sr Manager","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p>As a Sr. Manager of R&amp;D Engineering, you will lead a team of engineers in developing cutting-edge CMOS embedded memory technologies. You will be responsible for designing architecture and circuit implementation for ultra-high-speed, ultra-low-power, or high-density designs. You will also perform schematic entry, circuit simulation, layout planning, and supervision, as well as verify and validate designs to ensure high quality and performance.</p>\n<p>The ideal candidate will have a strong background in memory compiler development, with a minimum of 8-10 years of experience in CMOS memory design, circuit simulation, and memory layout design. You will also have experience with layout parasitic extraction and verification tools, as well as programming skills in C-Shell, Perl, C++, or JavaScript.</p>\n<p>As a leader, you will be responsible for mentoring and guiding a team of engineers, enhancing workflows and methodologies, and driving project success. You will also be expected to communicate effectively with cross-functional teams, including CAD and Frontend engineers, to automate memory compilers and generate EDA models.</p>\n<p>At Synopsys, we offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e76957dd-344","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/r-and-d-engineering-sr-manager/44408/93159885760","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS memory design","circuit simulation","memory layout design","layout parasitic extraction and verification tools","C-Shell","Perl","C++","JavaScript"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:43.393Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS memory design, circuit simulation, memory layout design, layout parasitic extraction and verification tools, C-Shell, Perl, C++, JavaScript"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_471316cf-932"},"title":"Analog Layout, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are hiring a Staff Engineer to lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n<p>As a Staff Engineer, you will be responsible for leading the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies. You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n<p>You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n<p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.</p>\n<p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.</p>\n<p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li><p>Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n</li>\n<li><p>Hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n</li>\n<li><p>Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n</li>\n<li><p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings.</p>\n</li>\n<li><p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.</p>\n</li>\n<li><p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.</p>\n</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li><p>BTech/MTech degree in Electrical Engineering, Electronics, or related field.</p>\n</li>\n<li><p>5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).</p>\n</li>\n<li><p>Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.</p>\n</li>\n<li><p>Strong understanding of floorplan techniques and deep submicron effects.</p>\n</li>\n<li><p>Proven ability to lead projects and deliver best product quality within tight timelines.</p>\n</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li><p>Collaborative and team-oriented, with a commitment to inclusion and diversity.</p>\n</li>\n<li><p>Detail-oriented, with strong problem-solving and analytical skills.</p>\n</li>\n<li><p>Effective communicator, both written and verbal, with excellent interpersonal abilities.</p>\n</li>\n<li><p>Adaptable and eager to learn, embracing new technologies and methodologies.</p>\n</li>\n<li><p>Empathetic mentor, fostering accountability, ownership, and technical growth in others.</p>\n</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li><p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n</li>\n<li><p>In addition to company holidays, we have ETO and FTO Programs.</p>\n</li>\n<li><p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n</li>\n<li><p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n</li>\n<li><p>Save for your future with our retirement plans that vary by region and country.</p>\n</li>\n<li><p>Competitive salaries.</p>\n</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_471316cf-932","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/analog-layout-staff-engineer/44408/92693931728","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","CMOS","FinFET","GAA process technologies","layout matching techniques","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":["collaborative and team-oriented","detail-oriented","effective communicator","adaptable and eager to learn","empathetic mentor"],"datePosted":"2026-04-05T13:21:26.995Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, CMOS, FinFET, GAA process technologies, layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements, collaborative and team-oriented, detail-oriented, effective communicator, adaptable and eager to learn, empathetic mentor"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a85bfb6-707"},"title":"Custom Analog Enablement and Methodology, Sr Staff Engineer","description":"<p>Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.</p>\n<p>As a Sr Staff Engineer in Custom Analog Enablement and Methodology, you will propose and develop advanced layout design techniques and methodologies, including specification, prototyping, and building solutions with scripting languages (Tcl/Perl/Python). You will run verification on existing designs to assess PDK update impacts and create innovative scripts to minimize rework. You will collaborate with multiple organizations and teams across global time zones to ensure the design environment is optimized for IP design teams.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Proposing and developing advanced layout design techniques and methodologies</li>\n<li>Running verification on existing designs to assess PDK update impacts</li>\n<li>Creating innovative scripts to minimize rework</li>\n<li>Collaborating with multiple organizations and teams across global time zones</li>\n</ul>\n<p>The ideal candidate will have a deep understanding of custom analog layout design, especially with sub-5nm FinFet/Gate-All-Around nodes. You will be proficient in scripting languages: Tcl, Perl, and Python for workflow automation and prototyping. You will also have the ability to debug LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports effectively.</p>\n<p>This role offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a85bfb6-707","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/mississauga/custom-analog-enablement-and-methodology-sr-staff-engineer-15402/44408/93442249536","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["custom analog layout design","sub-5nm FinFet/Gate-All-Around nodes","scripting languages: Tcl, Perl, Python","LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports"],"x-skills-preferred":["workflow automation and prototyping","collaboration with multiple organizations and teams across global time zones"],"datePosted":"2026-04-05T13:17:37.947Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Mississauga"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"custom analog layout design, sub-5nm FinFet/Gate-All-Around nodes, scripting languages: Tcl, Perl, Python, LVS (Layout Versus Schematic) and DRC (Design Rule Check) reports, workflow automation and prototyping, collaboration with multiple organizations and teams across global time zones"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1f955980-d4b"},"title":"Analog & Mixed-Signal Layout Designer","description":"<p>We are seeking a skilled Analog &amp; Mixed-Signal Layout Designer to join our IP Design Group in Lisbon. As a key member of our team, you will be responsible for designing and developing cutting-edge semiconductor solutions. You will work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>Collaborating with local and international teams to develop layouts for complex analog and mixed-signal designs in advanced technology nodes (3nm, 2nm, and beyond).</p>\n<p>Utilizing Synopsys suite of tools and full custom analog layout design tools (e.g., Custom Compiler) to create and optimize circuit layouts.</p>\n<p>Implementing and verifying designs using industry-leading verification tools such as ICV, Calibre and Star-RCXT...</p>\n<p>Developing SERDES sub-circuit layouts (RX, TX, PLL, etc.) and optimizing for signal integrity, including clock/data routes, differential routing, and shielding.</p>\n<p>Applying scripting techniques (TCL, Python, etc.) to automate layout processes and improve workflow efficiency.</p>\n<p>Ensuring designs meet ESD constraints, mitigate latch-up risks, and optimize for reliability issues such as EM and IR drop.</p>\n<p>Designing custom digital logic cell layouts and associated logic path routing for mixed-signal integration.</p>\n<p>Refining layouts to minimize parasitic effects and enhance matching, reliability, and performance.</p>\n<p>Delivering high-quality IP that powers next-generation semiconductor products for global customers.</p>\n<p>Enabling Synopsys to maintain leadership in advanced technology node design and IP development.</p>\n<p>Contributing to the creation of reliable, high-performance silicon chips used in communications.</p>\n<p>Driving innovation in analog and mixed-signal layout methodologies and tools.</p>\n<p>Enhancing cross-team collaboration and knowledge sharing to accelerate project timelines and improve outcomes.</p>\n<p>Ensuring robust design practices that minimize risk and maximize reliability, meeting stringent industry standards.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1f955980-d4b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/porto-salvo/analog-and-mixed-signal-layout-designer/44408/93465071552","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog and mixed-signal layout design","full custom analog layout tools","verification tools","scripting languages","custom digital layout and associated routing techniques"],"x-skills-preferred":["TCL","Python","ICV","Calibre","Star-RCXT"],"datePosted":"2026-04-05T13:16:48.393Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Porto Salvo"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog and mixed-signal layout design, full custom analog layout tools, verification tools, scripting languages, custom digital layout and associated routing techniques, TCL, Python, ICV, Calibre, Star-RCXT"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a1f10d9-1d4"},"title":"Analog Layout Design, Staff Engineer","description":"<p>We are seeking an experienced Analog Layout Staff Engineer to join our team in Hanoi. The successful candidate will be responsible for designing and developing high-performance analog IPs, including high-speed IOs, PLLs, DLLs, and bandgap circuits. The ideal candidate will have a strong background in custom layout design and experience with layout entry tools such as Cadence and Synopsys.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a1f10d9-1d4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/analog-layout-design-staff-engineer-in-hanoi/44408/90166587152","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["custom layout design","layout entry tools","high-speed layout techniques"],"x-skills-preferred":["ESD","Latchup","Antenna","EMIR"],"datePosted":"2026-03-06T07:30:48.971Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"custom layout design, layout entry tools, high-speed layout techniques, ESD, Latchup, Antenna, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_42cea958-a73"},"title":"Layout Design, Sr Engineer","description":"<p>We are seeking a skilled Layout Design, Sr Engineer to join our team in Da Nang. As a Layout Design, Sr Engineer, you will be responsible for designing and integrating memory leafcells and standard cell layouts, optimizing layouts for speed, area, and power, and collaborating with circuit and verification engineers.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Designing and integrating memory leafcells and standard cell layouts.</li>\n<li>Optimizing layouts for speed, area, and power.</li>\n<li>Running and debugging DRC, LVS, and ERC checks.</li>\n<li>Collaborating with circuit and verification engineers.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>2+ years in custom, standard cell, or memory layout design.</li>\n<li>Experience with FinFET, DRC, LVS, ERC, and boundary conditions.</li>\n<li>Proficiency in Custom Compiler, ICV, and scripting (Perl, Shell, TCL).</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_42cea958-a73","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/layout-design-sr-engineer-in-da-nang/44408/91405850624","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","FinFET","DRC","LVS","ERC"],"x-skills-preferred":["Custom Compiler","ICV","Perl","Shell","TCL"],"datePosted":"2026-03-06T07:24:58.328Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, FinFET, DRC, LVS, ERC, Custom Compiler, ICV, Perl, Shell, TCL"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_caa1b66e-3b3"},"title":"Layout Design, Staff Engineer","description":"<p>As a part of our team you will be responsible for delivering fully-verified, clean layout. This includes the following:</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>Crafting sophisticated layout for mixed signal and analog circuits in deep sub-micron CMOS technologies.</p>\n<ul>\n<li>Reviewing and analyzing floorplans and intricate circuits with circuit designers.</li>\n</ul>\n<ul>\n<li>Running complete sets of design verification tools available on AMS blocks.</li>\n</ul>\n<ul>\n<li>Working with the circuit design team to plan/schedule work and coordinate vital layout tradeoffs as needed.</li>\n</ul>\n<ul>\n<li>Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout.</li>\n</ul>\n<ul>\n<li>Exceeding engineering specifications and expectations by working closely with the circuit design team.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>B.Tech/M.Tech with 5+ years of relevant experience.</li>\n</ul>\n<ul>\n<li>Proven experience in analog/mixed-signal layout design of deep sub-micron CMOS circuits.</li>\n</ul>\n<ul>\n<li>Experience in implementing analog layouts to achieve tight matching, low noise, and low power consumption.</li>\n</ul>\n<ul>\n<li>High level of proficiency in custom and standard cell based floor-planning and hierarchical layout assembly.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_caa1b66e-3b3","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/pune/layout-design-staff-engineer/44408/92296851936","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["analog/mixed-signal layout design","deep sub-micron CMOS circuits","custom and standard cell based floor-planning"],"x-skills-preferred":["analog layouts","tight matching","low noise","low power consumption"],"datePosted":"2026-03-06T07:23:44.153Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Pune"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"analog/mixed-signal layout design, deep sub-micron CMOS circuits, custom and standard cell based floor-planning, analog layouts, tight matching, low noise, low power consumption"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ea6a34b3-c1d"},"title":"Staff Memory Layout Engineer","description":"<p>We are seeking a Staff Memory Layout Engineer to join our team. As a Staff Memory Layout Engineer, you will be responsible for leading the physical layout design of advanced memory IP (SRAM, ROM, eDRAM, etc.) at cell, array, and peripheral levels.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Lead the physical layout design of advanced memory IP (SRAM, ROM, eDRAM, etc.) at cell, array, and peripheral levels</li>\n<li>Ensure compliance with foundry process design rules (DRC/LVS) and memory-specific constraints</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics Engineering, Telecommunication, Physics, or related fields</li>\n<li>Minimum of 5 years of experience in layout design</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ea6a34b3-c1d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/staff-memory-layout-engineer-in-da-nang/44408/91391710096","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["layout design","foundry process design rules","memory-specific constraints"],"x-skills-preferred":["Custom Compiler","IC Compiler","Virtuoso"],"datePosted":"2026-03-06T07:23:16.436Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, foundry process design rules, memory-specific constraints, Custom Compiler, IC Compiler, Virtuoso"}]}