{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/latchup"},"x-facet":{"type":"skill","slug":"latchup","display":"Latchup","count":3},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_63c3f231-21b"},"title":"Analog Layout Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As an experienced Analog Layout Senior Engineer, you will work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield. You will build and enhance layout flow for faster, higher quality design processes.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees.</li>\n<li>Floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics.</li>\n<li>Apply Analog Layout techniques to ensure design meets performance with minimum area and good yield.</li>\n<li>Build and enhance layout flow for faster, higher quality design processes.</li>\n<li>Perform layout verification for DRC/LVS/ERC/ANT/ESD/DFM.</li>\n<li>Conduct PERC verification for ESD/LUP checks.</li>\n<li>Complete all design quality checks and data quality checks.</li>\n<li>Collaborate with Place and Route engineers to integrate analog layouts into the top level.</li>\n<li>Work with the Package team to ensure the integration of top die and package.</li>\n<li>Participate in design reviews across the global team.</li>\n<li>Engage in package design, including interposer and RDL design.</li>\n<li>Collaborate closely with design teams in Vietnam, USA, Canada, and other countries to ensure the success of the whole product.</li>\n<li>Join research programs to implement new ideas for future products and flows.</li>\n<li>Lead a layout team to complete a full design block.</li>\n<li>Mentor junior layout engineers or interns.</li>\n</ul>\n<p><strong>Impact</strong></p>\n<ul>\n<li>Drive the development of high-performance Analog IPs that power cutting-edge technologies.</li>\n<li>Enhance the layout design process for improved efficiency and quality.</li>\n<li>Ensure the robustness and reliability of our designs through meticulous verification processes.</li>\n<li>Contribute to the integration of complex layouts into top-level designs.</li>\n<li>Foster collaboration and knowledge sharing across global teams.</li>\n<li>Mentor and develop the next generation of layout engineers.</li>\n</ul>\n<p><strong>Requirements</strong></p>\n<ul>\n<li>BS in Electronics Engineering, Electromechanics, Telecommunications.</li>\n<li>2+ years of experience in custom layout.</li>\n<li>Proficiency with layout entry tools: Cadence, Synopsys.</li>\n<li>Experience with layout verification tools: Mentor Calibre, Synopsys ICV.</li>\n<li>Understanding of basic semiconductor fabrication processes and MOSFET fundamentals.</li>\n<li>Knowledge of high-speed layout techniques, ESD, Latchup, Antenna, EMIR.</li>\n<li>Experience mentoring/leading junior layout engineers.</li>\n<li>Ability to write layout review presentations and layout verification reports.</li>\n<li>Good English communication skills.</li>\n</ul>\n<p><strong>Team</strong></p>\n<p>You will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_63c3f231-21b","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/analog-layout-design-sr-engineer/44408/92879619712","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Cadence","Synopsys","Mentor Calibre","Synopsys ICV","Electronics Engineering","Electromechanics","Telecommunications","High-speed layout techniques","ESD","Latchup","Antenna","EMIR"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:34.005Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Cadence, Synopsys, Mentor Calibre, Synopsys ICV, Electronics Engineering, Electromechanics, Telecommunications, High-speed layout techniques, ESD, Latchup, Antenna, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5a1f10d9-1d4"},"title":"Analog Layout Design, Staff Engineer","description":"<p>We are seeking an experienced Analog Layout Staff Engineer to join our team in Hanoi. The successful candidate will be responsible for designing and developing high-performance analog IPs, including high-speed IOs, PLLs, DLLs, and bandgap circuits. The ideal candidate will have a strong background in custom layout design and experience with layout entry tools such as Cadence and Synopsys.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5a1f10d9-1d4","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/analog-layout-design-staff-engineer-in-hanoi/44408/90166587152","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["custom layout design","layout entry tools","high-speed layout techniques"],"x-skills-preferred":["ESD","Latchup","Antenna","EMIR"],"datePosted":"2026-03-06T07:30:48.971Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"custom layout design, layout entry tools, high-speed layout techniques, ESD, Latchup, Antenna, EMIR"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_a9af8bd7-647"},"title":"Senior/Staff - Analog Design Engineer","description":"<p>We currently have 349 open roles.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<p>You are an accomplished analog and mixed-signal design engineer, passionate about pushing the boundaries of high-speed interface technology. With a strong foundation in Electrical, Electronics, or VLSI Engineering, you have hands-on expertise in custom analog circuit design, particularly in the nanometer CMOS domain.</p>\n<ul>\n<li>Designing and developing high-speed analog and mixed-signal (AMS) circuit macros, including analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, regulators, equalizers (CTLE, FFE, DFE), impedance calibrators, serializers/deserializers, VCOs, phase interpolators, bandgap references, CDR circuits, and injection-locked loops for High-Speed PHY IP in planar and FinFET CMOS technologies.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s degree (BE) plus 3+ years or Master’s degree (MTech) plus 2+ years of relevant experience in mixed-signal analog/custom circuit design, preferably in Electrical/Electronics/VLSI Engineering.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_a9af8bd7-647","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/senior-staff-analog-design-engineer/44408/90941185632","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["CMOS circuit design fundamentals","device physics","layout","parasitic extraction","SPICE simulation","high-speed SERDES and PHY IP","digital/CMOS logic cells","ESD and latchup design verification","crosstalk analysis"],"x-skills-preferred":["advanced simulation tools","full custom design of high-speed datapaths","timing margins"],"datePosted":"2026-01-28T15:08:44.691Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida, Uttar Pradesh, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"CMOS circuit design fundamentals, device physics, layout, parasitic extraction, SPICE simulation, high-speed SERDES and PHY IP, digital/CMOS logic cells, ESD and latchup design verification, crosstalk analysis, advanced simulation tools, full custom design of high-speed datapaths, timing margins"}]}