{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/jtag"},"x-facet":{"type":"skill","slug":"jtag","display":"Jtag","count":12},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_57af9e4c-fa7"},"title":"Firmware Engineer, SPX","description":"<p>As a Firmware Engineer, you will focus on AMI SPX-based BMC firmware development for GB200 server platforms. You will collaborate with cross-functional teams to develop, enhance, and optimize embedded firmware modules that power CoreWeave&#39;s large-scale data center deployments.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Develop &amp; Maintain: Contribute to the design, implementation, and testing of BMC firmware in AMI SPX environments using C.</li>\n<li>Integrate: Work cross-functionally with hardware, software, and QA teams to ensure seamless firmware-hardware integration.</li>\n<li>Debug &amp; Optimize: Perform issue triage, root-cause analysis, and implement bug fixes and performance improvements.</li>\n<li>Testing &amp; Validation: Conduct firmware validation across multiple hardware revisions and test environments.</li>\n<li>Document: Produce clear and maintainable documentation for code, configurations, and testing procedures.</li>\n<li>Collaborate &amp; Learn: Work alongside senior engineers to expand your expertise in firmware stack design, Redfish, and system-level architecture.</li>\n</ul>\n<p>The base salary range for this role is $109,000 to $160,000. The starting salary will be determined based on job-related knowledge, skills, experience, and market location. We strive for both market alignment and internal equity when determining compensation. In addition to base salary, our total rewards package includes a discretionary bonus, equity awards, and a comprehensive benefits program (all based on eligibility).</p>\n<p>What We Offer: The range we&#39;ve posted represents the typical compensation range for this role. To determine actual compensation, we review the market rate for each candidate which can include a variety of factors. These include qualifications, experience, interview performance, and location.</p>\n<p>In addition to a competitive salary, we offer a variety of benefits to support your needs, including:</p>\n<ul>\n<li>Medical, dental, and vision insurance - 100% paid for by CoreWeave</li>\n<li>Company-paid Life Insurance</li>\n<li>Voluntary supplemental life insurance</li>\n<li>Short and long-term disability insurance</li>\n<li>Flexible Spending Account</li>\n<li>Health Savings Account</li>\n<li>Tuition Reimbursement</li>\n<li>Ability to Participate in Employee Stock Purchase Program (ESPP)</li>\n<li>Mental Wellness Benefits through Spring Health</li>\n<li>Family-Forming support provided by Carrot</li>\n<li>Paid Parental Leave</li>\n<li>Flexible, full-service childcare support with Kinside</li>\n<li>401(k) with a generous employer match</li>\n<li>Flexible PTO</li>\n<li>Catered lunch each day in our office and data center locations</li>\n<li>A casual work environment</li>\n<li>A work culture focused on innovative disruption</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_57af9e4c-fa7","directApply":true,"hiringOrganization":{"@type":"Organization","name":"CoreWeave","sameAs":"https://www.coreweave.com","logo":"https://logos.yubhub.co/coreweave.com.png"},"x-apply-url":"https://job-boards.greenhouse.io/coreweave/jobs/4615564006","x-work-arrangement":"hybrid","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$109,000 to $160,000","x-skills-required":["AMI MegaRAC/SPX firmware","C","embedded development workflows","Linux","Git","debugging tools (GDB, JTAG, or equivalent)","hardware interfaces (I2C, SPI, UART)","firmware build systems","BMC architectures","DMTF Redfish","IPMI standards"],"x-skills-preferred":["GB200 or other NVIDIA Grace Hopper server platforms","Python or Bash for testing or automation","Jenkins or similar CI/CD environments","open-source firmware or embedded projects"],"datePosted":"2026-04-18T15:49:12.401Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Livingston, NJ / New York, NY / Sunnyvale, CA / Bellevue, WA"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"AMI MegaRAC/SPX firmware, C, embedded development workflows, Linux, Git, debugging tools (GDB, JTAG, or equivalent), hardware interfaces (I2C, SPI, UART), firmware build systems, BMC architectures, DMTF Redfish, IPMI standards, GB200 or other NVIDIA Grace Hopper server platforms, Python or Bash for testing or automation, Jenkins or similar CI/CD environments, open-source firmware or embedded projects","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":109000,"maxValue":160000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c12edbfc-7a0"},"title":"DFT Junior Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>The role involves intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a DFT Junior Engineer, you will own DFT tasks, create timing constraints for mission and DFT modes, work with design and implementation teams, support customer IP integration and silicon bring-up, automate workflows with scripting, and mentor junior team members.</p>\n<p>The impact you will have includes enhancing IP core testability and quality, accelerating time-to-market for new chipsets, facilitating seamless SoC integration, promoting best practices and team growth, advancing DFT methodologies at Synopsys, and supporting customers during silicon bring-up.</p>\n<p>To be successful in this role, you will need a degree in Electronics, Electrical Engineering, or a related field, no DFT experience required for junior roles, knowledge of scan insertion, ATPG, JTAG, experience with Synopsys tools (Design Compiler, VCS, TetraMAX) preferred, and scripting skills (Perl, TCL, Python).</p>\n<p>You will be an analytical, detail-oriented, proactive, collaborative and communicative individual who is adaptable and eager to learn.</p>\n<p>Join a skilled DFT engineering team that values collaboration, innovation, and technical excellence. Benefit from mentorship and tackle industry-leading challenges together.</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will share more about salary and benefits during the process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c12edbfc-7a0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/dft-junior-engineer-in-hcmc-ha-noi-da-nang/44408/92864858752","x-work-arrangement":"onsite","x-experience-level":"entry","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","scripting skills (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:13.711Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), scripting skills (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3541c574-2ff"},"title":"Layout Design, Sr Manager","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.</p>\n<p>You Are:</p>\n<p>You are an accomplished engineering professional with a strong background in analog and mixed-signal circuit design. With over 12 years of industry experience, you have a deep understanding of circuit design fundamentals, device physics, and technology effects. You have successfully managed projects from specifications to silicon, and you are comfortable interfacing with both internal and external stakeholders. You are a proactive team player with excellent problem-solving skills and a knack for managing complex projects. Your high energy and flexible personality allow you to go the extra mile, fostering collaboration and driving projects to successful completion. You are adept at conflict resolution and possess strong customer-facing skills, making you an invaluable asset to any high-performing team.</p>\n<p>What You’ll Be Doing:</p>\n<p>Managing analog and mixed-signal IP projects from specifications to silicon.\nInteracting with customers to guide them and help adapt our solutions to their needs.\nHandling customer queries and debugging problems efficiently.\nAligning with and improving established design processes.\nInterfacing with internal and external stakeholders to ensure high engagement levels.\nCollaborating with a global team to co-develop Analog Full Custom IPs such as GPIOs, I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG, and more.</p>\n<p>The Impact You Will Have:</p>\n<p>Driving the integration of advanced capabilities into System on Chips (SoCs).\nEnabling customers to meet unique performance, power, and size requirements.\nAccelerating the time-to-market for differentiated products with reduced risk.\nEnhancing the design and development of high-performance silicon IP.\nImproving customer satisfaction through efficient problem-solving and support.\nContributing to the continuous innovation and technological advancements at Synopsys.</p>\n<p>What You’ll Need:</p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electrical Engineering or a related field from a reputed institution.\n12+ years of industry experience in analog and mixed-signal circuit design.\nProven experience in managing projects from specifications to silicon.\nStrong understanding of circuit design fundamentals, device physics, and technology effects.\nProficiency in spice simulations and various sub-micron design methodologies.</p>\n<p>Who You Are:</p>\n<p>A proactive team player with strong written and verbal communication skills.\nHigh energy individual with the ability to go the extra mile.\nCreative and flexible personality with excellent customer-facing skills.\nDemonstrates good analysis and problem-solving skills.\nAdept at conflict resolution and fostering collaboration among team members.</p>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You will be part of a strong development team specializing in GPIOs, Specialty IOs, and General Purpose Analog IPs. The team is distributed globally, bringing together experienced professionals from various sites. Together, you will co-develop high-performance analog full custom IPs and work on projects that push the boundaries of technology.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3541c574-2ff","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-manager/44408/93232526160","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog and mixed-signal circuit design","spice simulations","sub-micron design methodologies","GPIOs","I2C","I3C","SMBUS","eMMC","SVID","Quad SPI","JTAG"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:20.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog and mixed-signal circuit design, spice simulations, sub-micron design methodologies, GPIOs, I2C, I3C, SMBUS, eMMC, SVID, Quad SPI, JTAG"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7026ea72-dd8"},"title":"RTL Design, Sr Engineer","description":"<p>We are seeking a skilled RTL Design Engineer to join our team in Hanoi/Ho Chi Minh City/Da Nang. As a member of our team, you will be responsible for developing specifications and RTL for High Bandwidth Interface PHY IP. You will collaborate with Verification teams to ensure design accuracy and coordinate logic implementation phases across teams. You will also apply scripting skills for design automation and participate in onboarding in Da Nang and transitioning to Hanoi or Ho Chi Minh City.</p>\n<p>The successful candidate will have a BS/MS/PhD in Electronics Engineering or Telecommunications and 2+ years of experience in RTL design for ASIC or PHY IP. You will have experience with VCS, Verdi, Spyglass, Perl/TCL/Python and knowledge of clock domain crossing, APB, JTAG. Good English communication skills are essential.</p>\n<p>As a member of our team, you will advance industry-leading high bandwidth interface IP, ensure robust design and verification processes, drive innovation in RTL design and workflows, and enhance productivity through automation.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7026ea72-dd8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/rtl-design-sr-engineer-in-hanoi-hcmc-da-nang/44408/92454718896","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design","ASIC design","PHY IP","VCS","Verdi","Spyglass","Perl","TCL","Python","clock domain crossing","APB","JTAG"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:17.483Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, ASIC design, PHY IP, VCS, Verdi, Spyglass, Perl, TCL, Python, clock domain crossing, APB, JTAG"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_66c5c8aa-9e8"},"title":"Solutions Engineering, Sr Staff Engineer (DFT ,Verification, product Engineer)","description":"<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a dynamic engineer with working experience in RTL implementation, DFT, verification, flow automation and understanding of 3DIC solutions and UCIe protocols. You should have a passion for working with the best of the brains in the industry in developing end-to-end solutions and deploying them at our premier customer base. Your technical excellence and analytical skills, coupled with strong communication and interpersonal skills, make you an asset to any team.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li><p>Working closely with a world-class R&amp;D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM) and 3DIC technologies.</p>\n</li>\n<li><p>Working closely with customers, you will bring detailed requirements into the factory to enable R&amp;D for strong, robust, and successful product development.</p>\n</li>\n<li><p>Working closely with product development team, you will validate an end-to-end solution both internally (before shipment) as well as in customer environment.</p>\n</li>\n<li><p>Driving the deployment and smooth execution of SLM solutions into customers’ projects.</p>\n</li>\n<li><p>Enabling customers to realize the value of silicon health monitoring in the context of 3DIC systems throughout the lifecycle of silicon bring-up, validation, through in-field operations.</p>\n</li>\n</ul>\n<p>The impact you will have includes enhancing Synopsys’ Silicon Lifecycle Management (SLM) and 3DIC solutions’ IP portfolio and end-to-end solution especially in the growing field of multi-die (3DIC) domain, driving the adoption of Synopsys’ SLM and 3DIC solutions at premier customer base worldwide, and influencing the development of next-generation SLM IPs and solutions.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_66c5c8aa-9e8","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/solutions-engineering-sr-staff-engineer-dft-verification-product-engineer/44408/92871142528","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL design and verification","D2D and PHY protocols","UCIe and HBM","JTAG IEEE 1149.1","IEEE 1687/1500","BIST/DFT mechanisms","3D-IC/2.5D-IC solutions","IEEE 1838 and UCIe standards","PCIe & USB protocol knowledge","Debugging abilities","Flow automation","Synthesis","Lint, CDC, RDC"],"x-skills-preferred":["GenAI and Agentic AI workflows","Architecture/micro-architecture experience","Understanding of GenAI and Agentic AI workflows"],"datePosted":"2026-04-05T13:21:31.895Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design and verification, D2D and PHY protocols, UCIe and HBM, JTAG IEEE 1149.1, IEEE 1687/1500, BIST/DFT mechanisms, 3D-IC/2.5D-IC solutions, IEEE 1838 and UCIe standards, PCIe & USB protocol knowledge, Debugging abilities, Flow automation, Synthesis, Lint, CDC, RDC, GenAI and Agentic AI workflows, Architecture/micro-architecture experience, Understanding of GenAI and Agentic AI workflows"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c9605b6a-5ba"},"title":"DFT Senior/Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a DFT Senior/Staff Engineer, you will own DFT tasks at IP level, including scan chain stitching, ATPG, and simulation. You will create timing constraints for mission and DFT modes, work with design and physical implementation teams on synthesis and constraint validation, support customer IP integration and silicon bring-up, and lead and coach DFT team members.</p>\n<p>The impact you will have includes improving testability and quality of IP cores, speeding up time-to-market for new chips, supporting seamless SoC integrations for customers, and mentoring team members and sharing best practices.</p>\n<p>To be successful in this role, you will need a BS/MS/PhD in Electronics or a related field, 2+ years DFT design experience, expertise in scan insertion, ATPG, JTAG, and experience with Synopsys tools (Design Compiler, VCS, TetraMAX) is a plus. You will also need scripting skills (Perl, TCL, Python) and be detail-oriented, analytical, and a strong communicator.</p>\n<p>Join our expert DFT Engineering team in Ho Chi Minh City, dedicated to advancing testability and reliability in semiconductor IP.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c9605b6a-5ba","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/dft-senior-staff-engineer-in-hcmc-ha-noi-da-nang/44408/90071446368","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["scan insertion","ATPG","JTAG","Synopsys tools","scripting skills"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:48.960Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"scan insertion, ATPG, JTAG, Synopsys tools, scripting skills"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_85ea872e-b5f"},"title":"RTL Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.</p>\n<p>With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.</p>\n<p>Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.</p>\n<p>You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.</li>\n</ul>\n<ul>\n<li>Define synthesis constraints and resolve STA and gate-level simulation issues.</li>\n</ul>\n<ul>\n<li>Collaborate with verification, controller, and lab teams for design and debugging.</li>\n</ul>\n<ul>\n<li>Support RTL to GDS flow during logic implementation.</li>\n</ul>\n<ul>\n<li>Lead projects and train junior engineers.</li>\n</ul>\n<ul>\n<li>Work with customers to resolve technical RTL issues.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver robust RTL designs for advanced silicon solutions.</li>\n</ul>\n<ul>\n<li>Drive successful project completion and tape-outs.</li>\n</ul>\n<ul>\n<li>Enhance design quality and verification efficiency.</li>\n</ul>\n<ul>\n<li>Support customer success and strengthen Synopsys’ reputation.</li>\n</ul>\n<ul>\n<li>Mentor and grow engineering talent within the team.</li>\n</ul>\n<ul>\n<li>Contribute to digital flow improvements and innovation.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering or Telecommunications.</li>\n</ul>\n<ul>\n<li>5+ years of RTL design experience for ASIC or PHY IP.</li>\n</ul>\n<ul>\n<li>Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).</li>\n</ul>\n<ul>\n<li>Knowledge of clock domain crossing, APB, JTAG protocols.</li>\n</ul>\n<ul>\n<li>Strong English communication skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Responsible, result-oriented, and self-motivated.</li>\n</ul>\n<ul>\n<li>Collaborative and proactive problem solver.</li>\n</ul>\n<ul>\n<li>Effective communicator and mentor.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a collaborative engineering team delivering innovative PHY IP solutions.</p>\n<p>Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits.</p>\n<p>Your recruiter will provide more details about salary and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_85ea872e-b5f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/rtl-design-staff-engineer-in-hcmc-da-nang-hanoi/44408/92454718864","x-work-arrangement":"Onsite","x-experience-level":"Staff","x-job-type":"Employee","x-salary-range":null,"x-skills-required":["RTL design","ASIC or PHY IP development","VCS","Verdi","Spyglass","Perl","TCL","Python","Clock domain crossing","APB","JTAG protocols"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:30.225Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, ASIC or PHY IP development, VCS, Verdi, Spyglass, Perl, TCL, Python, Clock domain crossing, APB, JTAG protocols"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_335f783d-2a0"},"title":"Senior System Software Engineer, Client Embedded Controller","description":"<p>We are looking for a strong technical Firmware engineer to own firmware development for embedded controllers. You will work with various stakeholders internally and externally, to understand requirements, implement features, debug issues, and provide technical support to partners and customers.</p>\n<p><strong>Role Details:</strong></p>\n<ul>\n<li>Designing, implementing, and delivering Embedded Controller (EC) firmware for client devices</li>\n<li>Integration of EC firmware with other platform firmware</li>\n<li>Providing technical support to the EC Chip vendors and OEMs/ODMs</li>\n<li>Partnering with the EC Chip vendors to ensure products work best with NVIDIA products</li>\n<li>Working with hardware teams to review HW architecture &amp; schematics</li>\n<li>Collaborating with QA/Test architects to produce proper test tools and automation for qualifying firmware</li>\n<li>Developing collaterals for EC chip vendors and OEMs/ODMs</li>\n</ul>\n<p><strong>Requirements:</strong></p>\n<ul>\n<li>Bachelor’s Degree or higher in Electrical Engineering or Computer Science (or equivalent experience), and 5+ yrs of proven experience, with demonstrated strong ability as individual contributor</li>\n<li>Experience implementing firmware in ARM Architecture</li>\n<li>Experience implementing system software in a Linux OS environment</li>\n<li>Experience implementing Embedded Controller (EC) firmware</li>\n<li>Solid experience in C/C++ development</li>\n<li>Solid understanding of low-level interfaces like GPIO/I2C/SPI/eSPI/PCIe/JTAG etc. PCIe enumeration, IO at platform level for notebooks</li>\n<li>Experience working closely with HW teams, ODMs and vendors to introduce and support notebooks</li>\n<li>Background in python for scripting, and debugging skills in embedded Linux operating environments</li>\n<li>Excellent written and oral communication skills, good work ethics, high sense of teamwork, love to produce quality work and a commitment to finish your tasks every single day</li>\n</ul>\n<p><strong>Nice to Have:</strong></p>\n<ul>\n<li>Experience in Zephyr OS</li>\n<li>Expertise in Arm embedded architecture</li>\n<li>Experience in supporting Windows on Arm platforms</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_335f783d-2a0","directApply":true,"hiringOrganization":{"@type":"Organization","name":"NVIDIA","sameAs":"https://nvidia.wd5.myworkdayjobs.com","logo":"https://logos.yubhub.co/nvidia.com.png"},"x-apply-url":"https://nvidia.wd5.myworkdayjobs.com/en-US/NVIDIAExternalCareerSite/job/Taiwan-Taipei/Senior-System-Software-Engineer--Client-Embedded-Controller_JR2013136-1","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Firmware development","Embedded Controller (EC) firmware","ARM Architecture","Linux OS environment","C/C++ development","Low-level interfaces","GPIO/I2C/SPI/eSPI/PCIe/JTAG","Python scripting","Embedded Linux operating environments"],"x-skills-preferred":["Zephyr OS","Arm embedded architecture","Windows on Arm platforms"],"datePosted":"2026-03-09T20:45:55.651Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Taipei, Hsinchu"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Firmware development, Embedded Controller (EC) firmware, ARM Architecture, Linux OS environment, C/C++ development, Low-level interfaces, GPIO/I2C/SPI/eSPI/PCIe/JTAG, Python scripting, Embedded Linux operating environments, Zephyr OS, Arm embedded architecture, Windows on Arm platforms"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_b4e4a0dc-158"},"title":"DFT, Staff Engineer","description":"<p><strong>Overview</strong></p>\n<p>At Synopsys, our Hardware Engineers are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p><strong>Category</strong></p>\n<p>Engineering</p>\n<p><strong>Hire Type</strong></p>\n<p>Employee</p>\n<p><strong>Job ID</strong></p>\n<p>15995</p>\n<p><strong>Remote Eligible</strong></p>\n<p>No</p>\n<p><strong>Date Posted</strong></p>\n<p>03/05/2026</p>\n<p><strong>Alternate Job Titles:</strong></p>\n<ul>\n<li>Staff ASIC Digital Design Engineer</li>\n</ul>\n<ul>\n<li>Staff DFT Engineer</li>\n</ul>\n<ul>\n<li>Staff SoC Testability Engineer</li>\n</ul>\n<p><strong>We Are:</strong></p>\n<p>At Synopsys, we drive innovations that shape the way we live and connect. From smart cars to AI, our technology leads chip design and verification worldwide. Join us to transform the future through continuous innovation.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a proactive engineer with 5+ years of DFT experience, strong communication skills, and a drive for technical excellence. You enjoy teamwork, learning, and solving complex challenges in digital design.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Define and implement DFT architecture for IP designs</li>\n</ul>\n<ul>\n<li>Perform SCAN insertion and ATPG simulation</li>\n</ul>\n<ul>\n<li>Analyze and improve test coverage</li>\n</ul>\n<ul>\n<li>Develop STA DFT timing constraints</li>\n</ul>\n<ul>\n<li>Prepare DFT integration guidelines for SoC</li>\n</ul>\n<ul>\n<li>Conduct quality checks and FMEDA/DFMEA analysis</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Enhance product reliability and quality</li>\n</ul>\n<ul>\n<li>Support functional safety standards (ISO26262, FUSA)</li>\n</ul>\n<ul>\n<li>Streamline SoC integration</li>\n</ul>\n<ul>\n<li>Reduce debug cycles and time-to-market</li>\n</ul>\n<ul>\n<li>Mentor peers</li>\n</ul>\n<ul>\n<li>Drive innovation in test methodology</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics or related field</li>\n</ul>\n<ul>\n<li>5+ years DFT design experience</li>\n</ul>\n<ul>\n<li>Expertise in Scan insertion, ATPG, JTAG</li>\n</ul>\n<ul>\n<li>Experience with Synopsys tools (Design Compiler, VCS, TetraMAX)</li>\n</ul>\n<ul>\n<li>Scripting (Perl, TCL, Python) is a plus</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Responsible and collaborative</li>\n</ul>\n<ul>\n<li>Excellent English communication</li>\n</ul>\n<ul>\n<li>Team player and problem solver</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong></p>\n<p>Join a skilled, diverse engineering team in Da Nang focused on advancing DFT methodologies and supporting global innovation.</p>\n<p><strong>Rewards and Benefits:</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>### Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>\\<em>\\</em> Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_b4e4a0dc-158","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hanoi/dft-staff-engineer-in-hcmc-hanoi/44408/92454718736","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["DFT design experience","Scan insertion","ATPG","JTAG","Synopsys tools (Design Compiler, VCS, TetraMAX)","Scripting (Perl, TCL, Python)"],"x-skills-preferred":[],"datePosted":"2026-03-08T22:19:13.522Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hanoi"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"DFT design experience, Scan insertion, ATPG, JTAG, Synopsys tools (Design Compiler, VCS, TetraMAX), Scripting (Perl, TCL, Python)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d7d03868-78f"},"title":"Firmware Engineer, Robotics","description":"<p><strong>Job Posting</strong></p>\n<p><strong>Firmware Engineer, Robotics</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Location Type</strong></p>\n<p>On-site</p>\n<p><strong>Department</strong></p>\n<p>Research</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>$185K – $268K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the physical constraints of real-world systems to improve people’s lives.</p>\n<p><strong>About the Role</strong></p>\n<p>As a Firmware Engineer on the Robotics team, you will help enable the next generation of embodied AI by developing low-level firmware that drives our robotic systems. You will join at an early phase of our firmware development, working alongside electrical, mechanical, and control systems engineers to bring up new boards, integrate novel sensors, and build foundational infrastructure for the distributed system that drives our robots.</p>\n<p>This role is hands-on and bare-metal focused. You will read datasheets and reference manuals, write startup code and peripheral drivers, and debug hardware–firmware interactions during board bring-up and deployment. Your work will span everything from simple single-purpose sensing devices to more complex, safety- and reliability-critical subsystems, with an emphasis on correctness, performance, and scalability.</p>\n<p>By working closely across disciplines, you will help ensure that firmware, hardware, and system-level assumptions align, and that new designs can be brought up, tested, and iterated on quickly. This role offers a unique opportunity to shape the early firmware architecture for advanced robotic systems operating in real-world environments.</p>\n<p>This role is based in San Francisco, CA, and requires in-person presence 4 days a week.</p>\n<p><strong>You might thrive in this role if you:</strong></p>\n<ul>\n<li>Have experience developing firmware for microcontrollers and enjoy working close to the hardware.</li>\n</ul>\n<ul>\n<li>Are comfortable writing bare-metal firmware, or are eager to deepen your understanding of startup code, peripheral drivers, low-level system initialization, and bootloaders.</li>\n</ul>\n<ul>\n<li>Regularly read datasheets, reference manuals, and schematics to understand how new hardware works.</li>\n</ul>\n<ul>\n<li>Have participated in board bring-up, lab debugging, or early hardware validation.</li>\n</ul>\n<ul>\n<li>Are curious about how systems fail and enjoy debugging hardware-firmware interactions using real measurement tools.</li>\n</ul>\n<ul>\n<li>Are comfortable developing in a test-driven environment as well as building testbenches or simple tooling to validate hardware and system behavior.</li>\n</ul>\n<ul>\n<li>Care about writing correct, robust firmware and improving your technical judgment through hands-on experience.</li>\n</ul>\n<p><strong>Additional, preferred qualifications:</strong></p>\n<ul>\n<li>A Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field.</li>\n</ul>\n<ul>\n<li>Experience with common embedded communication protocols (e.g., SPI, I²C, UART, CAN, Ethernet, BiSS).</li>\n</ul>\n<ul>\n<li>Experience writing C++, or Rust for microcontrollers, especially in resource-constrained or bare-metal environments.</li>\n</ul>\n<ul>\n<li>Familiarity with hardware debugging tools such as JTAG/SWD, logic analyzers, oscilloscopes, or similar lab equipment.</li>\n</ul>\n<ul>\n<li>Experience with robotics, sensing systems, data acquisition, or other hardware-centric products.</li>\n</ul>\n<ul>\n<li>Clear written and verbal communication skills, especially when collaborating with hardware and systems engineers.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d7d03868-78f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/3f99bfef-5b1a-48ea-aed0-2dbd57b12722","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":"$185K – $268K • Offers Equity","x-skills-required":["Firmware development","Microcontrollers","Embedded communication protocols","C++","Rust","Hardware debugging tools","Robotics","Sensing systems","Data acquisition"],"x-skills-preferred":["SPI","I²C","UART","CAN","Ethernet","BiSS","JTAG/SWD","Logic analyzers","Oscilloscopes"],"datePosted":"2026-03-06T18:41:50.411Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Firmware development, Microcontrollers, Embedded communication protocols, C++, Rust, Hardware debugging tools, Robotics, Sensing systems, Data acquisition, SPI, I²C, UART, CAN, Ethernet, BiSS, JTAG/SWD, Logic analyzers, Oscilloscopes","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":185000,"maxValue":268000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_d4efa5c8-cef"},"title":"Offensive Security Engineer, Hardware","description":"<p><strong>Job Posting</strong></p>\n<p><strong>Offensive Security Engineer, Hardware</strong></p>\n<p><strong>Location</strong></p>\n<p>San Francisco</p>\n<p><strong>Employment Type</strong></p>\n<p>Full time</p>\n<p><strong>Department</strong></p>\n<p>Security</p>\n<p><strong>Compensation</strong></p>\n<ul>\n<li>San Francisco$293K – $490K • Offers Equity</li>\n</ul>\n<p>The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.</p>\n<ul>\n<li>Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts</li>\n</ul>\n<ul>\n<li>Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)</li>\n</ul>\n<ul>\n<li>401(k) retirement plan with employer match</li>\n</ul>\n<ul>\n<li>Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)</li>\n</ul>\n<ul>\n<li>Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees</li>\n</ul>\n<ul>\n<li>13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)</li>\n</ul>\n<ul>\n<li>Mental health and wellness support</li>\n</ul>\n<ul>\n<li>Employer-paid basic life and disability coverage</li>\n</ul>\n<ul>\n<li>Annual learning and development stipend to fuel your professional growth</li>\n</ul>\n<ul>\n<li>Daily meals in our offices, and meal delivery credits as eligible</li>\n</ul>\n<ul>\n<li>Relocation support for eligible employees</li>\n</ul>\n<ul>\n<li>Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.</li>\n</ul>\n<p>More details about our benefits are available to candidates during the hiring process.</p>\n<p>This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.</p>\n<p><strong>About the Team</strong></p>\n<p>Security is at the foundation of OpenAI’s mission to ensure that artificial general intelligence benefits all of humanity. The Security team protects OpenAI’s technology, people, and products. We are technical in what we build but are operational in how we do our work, and are committed to supporting all products and research at OpenAI. Our Security team tenets include: prioritizing for impact, enabling researchers, preparing for future transformative technologies, and engaging a robust security culture.</p>\n<p><strong>About the Role</strong></p>\n<p>We&#39;re seeking an exceptional Principal-level Offensive Security Engineer to challenge and strengthen OpenAI&#39;s security posture. This role isn&#39;t your typical red team job - it&#39;s an opportunity to engage broadly and deeply, craft innovative attack simulations, collaborate closely with defensive teams, and influence strategic security improvements across the organization.</p>\n<p>You&#39;ll have the chance to not only find vulnerabilities but actively drive their resolution, automate offensive techniques with cutting-edge technologies, and use your unique attacker perspective to shape our security strategy. This role will be primarily focused on continuously testing our hardware products and related services.</p>\n<p><strong>In this role you will:</strong></p>\n<ul>\n<li>Collaborate proactively with engineering teams to enhance security and mitigate risks in hardware, firmware, and software.</li>\n</ul>\n<ul>\n<li>Perform comprehensive penetration testing on our diverse suite of products.</li>\n</ul>\n<ul>\n<li>Leverage advanced automation and OpenAI technologies to optimize your offensive security work.</li>\n</ul>\n<ul>\n<li>Present insightful, actionable findings clearly and compellingly to inspire impactful change.</li>\n</ul>\n<ul>\n<li>Influence security strategy by providing attacker-driven insights into risk and threat modeling.</li>\n</ul>\n<p><strong>You might thrive in this role if you have:</strong></p>\n<ul>\n<li>7+ years of hands-on experience or exceptional accomplishments demonstrating equivalent expertise.</li>\n</ul>\n<ul>\n<li>Exceptional skill in code review, identifying novel and subtle vulnerabilities.</li>\n</ul>\n<ul>\n<li>Demonstrated mastery assessing complex technology stacks, including:</li>\n</ul>\n<ul>\n<li>Proven ability to reverse engineer bootrom images, firmware, or silicon-level components.</li>\n</ul>\n<ul>\n<li>Deep familiarity with low-level kernel operations, secure boot processes, and hardware-software interactions.</li>\n</ul>\n<ul>\n<li>Hands-on experience building and validating secure boot chains and threat models.</li>\n</ul>\n<ul>\n<li>Proficiency with hardware debugging tools (UART, JTAG, SWD, oscilloscopes, logic analyzers).</li>\n</ul>\n<ul>\n<li>Solid programming skills in C/C++, Python, or assembly for embedded systems.</li>\n</ul>\n<ul>\n<li>Industry experience securing consumer hardware (e.g., mobile devices, IoT, chipsets).</li>\n</ul>\n<ul>\n<li>Excellent written and verbal communication skills for technical and non-technical audiences.</li>\n</ul>\n<ul>\n<li>Strong intuitive understanding of trust boundaries and risk assessment in dynamic contexts.</li>\n</ul>\n<ul>\n<li>Excellent coding skills, capable of writing robust tools and automation for offensive operations.</li>\n</ul>\n<ul>\n<li>Ability to communicate complex technical concepts effectively through compelling storytelling.</li>\n</ul>\n<ul>\n<li>Proven track record of not just finding vulnerabilities but actively contributing to solutions in complex codebases.</li>\n</ul>\n<p><strong>Bonus points:</strong></p>\n<ul>\n<li>Prior experience working in tech startups or fast-paced technology environments.</li>\n</ul>\n<ul>\n<li>Experience in related disciplines such as Software Engineering (SWE), Detection Engineering, Site Reliability Engineering (SRE), Security Engineering, or IT Infrastructure.</li>\n</ul>\n<p><strong>About OpenAI</strong></p>\n<p>OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives and experiences of our team members.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_d4efa5c8-cef","directApply":true,"hiringOrganization":{"@type":"Organization","name":"OpenAI","sameAs":"https://jobs.ashbyhq.com","logo":"https://logos.yubhub.co/openai.com.png"},"x-apply-url":"https://jobs.ashbyhq.com/openai/f123bbe4-7f19-46c8-a6ab-4a5d7b714988","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$293K – $490K","x-skills-required":["code review","penetration testing","advanced automation","secure boot processes","hardware debugging tools","C/C++","Python","assembly","embedded systems","consumer hardware","firmware","silicon-level components","low-level kernel operations","secure boot chains","threat models","UART","JTAG","SWD","oscilloscopes","logic analyzers","solid programming skills","industry experience","excellent written and verbal communication skills","trust boundaries","risk assessment","dynamic contexts","compelling storytelling","complex technical concepts","offensive operations","robust tools and automation"],"x-skills-preferred":["tech startups","fast-paced technology environments","Software Engineering","Detection Engineering","Site Reliability Engineering","Security Engineering","IT Infrastructure"],"datePosted":"2026-03-06T18:29:30.545Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"San Francisco"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"code review, penetration testing, advanced automation, secure boot processes, hardware debugging tools, C/C++, Python, assembly, embedded systems, consumer hardware, firmware, silicon-level components, low-level kernel operations, secure boot chains, threat models, UART, JTAG, SWD, oscilloscopes, logic analyzers, solid programming skills, industry experience, excellent written and verbal communication skills, trust boundaries, risk assessment, dynamic contexts, compelling storytelling, complex technical concepts, offensive operations, robust tools and automation, tech startups, fast-paced technology environments, Software Engineering, Detection Engineering, Site Reliability Engineering, Security Engineering, IT Infrastructure","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":293000,"maxValue":490000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cb4886f7-dde"},"title":"SoC Firmware-Hardware Validation Engineer","description":"<p>We are seeking a SoC Firmware-Hardware Validation Engineer to join our team in Lisbon. As a key member of our R&amp;D team, you will be responsible for conducting comprehensive testing on silicon implementations of high-speed analog integrated circuits in a cutting-edge R&amp;D lab environment.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Conducting comprehensive testing on silicon implementations of high-speed analog integrated circuits in a cutting-edge R&amp;D lab environment.</li>\n<li>Reviewing and debugging silicon under test, as well as supporting associated hardware systems to ensure optimal performance.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor’s degree in Electrical Engineering (BSEE) or equivalent technical field with at least 3+ years of industry direct related experience.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cb4886f7-dde","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/porto-salvo/soc-firmware-hardware-validation-engineer/44408/92358709488","x-work-arrangement":"onsite","x-experience-level":"mid","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["analog IC circuit knowledge","silicon validation","debugging complex hardware systems","Python for test automation and data analysis","FPGA programming (Verilog)"],"x-skills-preferred":["interface protocols such as PCI Express and Ethernet","NRZ and PAM4 encoding","communication interfaces (JTAG, I2C, SPI)"],"datePosted":"2026-03-04T17:07:18.030Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Porto Salvo, Lisbon District, Portugal"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"analog IC circuit knowledge, silicon validation, debugging complex hardware systems, Python for test automation and data analysis, FPGA programming (Verilog), interface protocols such as PCI Express and Ethernet, NRZ and PAM4 encoding, communication interfaces (JTAG, I2C, SPI)"}]}