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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_85ea872e-b5f"},"title":"RTL Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>We are seeking an experienced RTL design engineer with a strong background in electronics or telecommunications.</p>\n<p>With over five years in ASIC or PHY IP development, you’re passionate about solving technical challenges, collaborating with cross-functional teams, and mentoring others.</p>\n<p>Your communication skills and attention to detail ensure projects run smoothly from specification to silicon debug.</p>\n<p>You thrive in fast-paced environments and are eager to contribute to groundbreaking technology.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Develop RTL specifications and architectures for High Bandwidth Interface PHY IP.</li>\n</ul>\n<ul>\n<li>Define synthesis constraints and resolve STA and gate-level simulation issues.</li>\n</ul>\n<ul>\n<li>Collaborate with verification, controller, and lab teams for design and debugging.</li>\n</ul>\n<ul>\n<li>Support RTL to GDS flow during logic implementation.</li>\n</ul>\n<ul>\n<li>Lead projects and train junior engineers.</li>\n</ul>\n<ul>\n<li>Work with customers to resolve technical RTL issues.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Deliver robust RTL designs for advanced silicon solutions.</li>\n</ul>\n<ul>\n<li>Drive successful project completion and tape-outs.</li>\n</ul>\n<ul>\n<li>Enhance design quality and verification efficiency.</li>\n</ul>\n<ul>\n<li>Support customer success and strengthen Synopsys’ reputation.</li>\n</ul>\n<ul>\n<li>Mentor and grow engineering talent within the team.</li>\n</ul>\n<ul>\n<li>Contribute to digital flow improvements and innovation.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>BS/MS/PhD in Electronics Engineering or Telecommunications.</li>\n</ul>\n<ul>\n<li>5+ years of RTL design experience for ASIC or PHY IP.</li>\n</ul>\n<ul>\n<li>Expertise in VCS, Verdi, Spyglass, and scripting (Perl, TCL, Python).</li>\n</ul>\n<ul>\n<li>Knowledge of clock domain crossing, APB, JTAG protocols.</li>\n</ul>\n<ul>\n<li>Strong English communication skills.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Responsible, result-oriented, and self-motivated.</li>\n</ul>\n<ul>\n<li>Collaborative and proactive problem solver.</li>\n</ul>\n<ul>\n<li>Effective communicator and mentor.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>Join a collaborative engineering team delivering innovative PHY IP solutions.</p>\n<p>Work alongside experts in Ho Chi Minh City, Da Nang, or Hanoi, and contribute to Synopsys’ global leadership in semiconductor technology.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits.</p>\n<p>Your recruiter will provide more details about salary and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_85ea872e-b5f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/rtl-design-staff-engineer-in-hcmc-da-nang-hanoi/44408/92454718864","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"Employee","x-salary-range":null,"x-skills-required":["RTL design","ASIC or PHY IP development","VCS","Verdi","Spyglass","Perl","TCL","Python","Clock domain crossing","APB","JTAG protocols"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:20:30.225Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL design, ASIC or PHY IP development, VCS, Verdi, Spyglass, Perl, TCL, Python, Clock domain crossing, APB, JTAG protocols"}]}