We are hiring in Ottawa, ON and Mississauga, ON.

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars, machine learning to artificial intelligence. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

We develop and deliver industry-leading high-speed interface IP and system solutions, enabling customers to build reliable, high-performance products across advanced nodes and packaging technologies. Our Signal & Power Integrity (SIPI) team partners across silicon design, package design, board design, and validation teams to ensure robust SerDes links and power delivery in complex system environments.

You are a highly skilled and passionate engineer with a deep understanding of high-speed signal and power integrity, particularly in the realm of SerDes interfaces. With a proven track record in end-to-end SIPI for advanced links such as PCI Express (Gen6/7/8), E224G, E448G, and CXL (over PCIe), you thrive on solving complex engineering challenges and collaborating across cross-functional teams.

As a technical leader, you mentor others, drive technical reviews, and are committed to sharing your knowledge and standardizing best practices. Your disciplined approach to documentation and reproducibility ensures that learnings are captured and reused.

Responsibilities

• Lead end-to-end SIPI for high-speed interfaces including PCI Express (Gen6/7/8), E224G, E448G, CXL (over PCIe), and other SerDes interfaces, spanning on-die, interposer, package, PCB, connectors, and compliance fixtures.

• Drive channel modeling and correlation across time- and frequency-domain analysis: S-parameters, TDR, crosstalk, ICN/ccICN, ERL/dERL, jitter/noise budgeting, equalization tradeoffs (TX/RX FFE/DFE/CTLE), eye margin simulation, and link margining.

• Own and execute SI signoff methodology for SerDes channels, including test chip package/board SIPI model extraction/model quality checks, de-embedding, and ensuring models are bandwidth-appropriate for target data rates.

• Partner with circuit/PHY, interposer/package, board, and product teams to diagnose bring-up and lab issues; propose design fixes and quantify risk/benefit via simulation and measurement.

• Plan and run correlation experiments (bench characterization, compliance testing support, fixture design guidance) and document learnings as reusable design guidelines.

• Define, improve, and document SIPI flows, requirements, and checklists for internal teams and (where applicable) customers; mentor engineers and lead technical reviews.

• Provide technical leadership across programs: set priorities, identify cross-project reuse opportunities, and influence architecture choices impacting signal integrity and power integrity.

Impact

• Enable first-pass success of high-speed SerDes IP and system integrations by defining robust SIPI signoff criteria and delivering validated, correlated methodologies.

• Reduce schedule risk by rapidly diagnosing complex cross-domain issues (silicon/package/board/lab) and guiding practical design changes backed by quantitative analysis.

• Raise the technical bar by mentoring others, standardizing best practices, and influencing architectural decisions for next-generation interconnects.

• Improve product performance and reliability by ensuring thorough modeling, simulation, and correlation to hardware in diverse environments.

• Drive innovation in SIPI methodologies, enabling scalable, reusable flows across multiple programs and product lines.

• Foster a culture of collaboration and continuous improvement within the team and across partnering organizations.

Requirements

• B.S. (M.S./Ph.D. preferred) in Electrical/Electronics Engineering or related field.

• 10+ years of relevant experience in high-speed SI/PI for SerDes links (silicon + package + board), preferably in interface IP or high-volume product development.

• Strong fundamentals in EM, transmission lines, passive/active modeling, and statistical link analysis; comfortable translating system requirements into measurable/signoff criteria.

• Expertise with high-speed link concepts: insertion/return loss, impedance control, mode conversion, NEXT/FEXT, jitter/noise sources, equalization, BER, etc.

• Hands-on experience with modeling, simulation, and EM tools (HSPICE, Keysight ADS/SysteVue, Ansys HFSS/SIwave/AEDT, Cadence Sigrity, Mathworks SIMULINK) and model formats (Touchstone, IBIS-AMI, SPICE, EM-based RLGC).

• Experience with lab correlation and measurement techniques (TDR, VNA, eye/jitter measurements, de-embedding/fixture calibration) and working alongside validation/compliance teams.

• Proficiency in scripting/automation for flow enablement (Python preferred; MATLAB/TCL a plus) and a disciplined approach to documentation and reproducibility.

• Demonstrated technical leadership: mentoring, design reviews, influencing cross-functional decisions, and communicating complex topics clearly to mixed audiences.

Who You Are

• Analytical and detail-oriented, with a passion for tackling complex engineering challenges.

• Collaborative and communicative, able to work effectively across multi-disciplinary teams.

• Proactive and resourceful, constantly seeking opportunities to optimize processes and drive innovation.

• Mentor and leader, committed to sharing knowledge and empowering others.

• Disciplined and organized, with a strong focus on documentation, reproducibility, and best practices.

• Adaptable, able to thrive in fast-paced, dynamic environments.

The Team You’ll Be Part Of

You will join a global SIPI team that works closely with SerDes/PHY design, package and board engineering, validation, and product teams to deliver high-performance interface IP. The team values rigorous analysis, strong correlation to hardware, and practical engineering judgment. Together, we drive innovation and enable our customers to create high-performance silicon chips and software content.

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We're building the infrastructure that lets people talk to Claude,real-time, bidirectional voice conversations that feel natural, responsive, and safe. This is foundational work for how millions of people will interact with AI.

The Voice Platform team designs and operates the serving systems, streaming pipelines, and APIs that bring Anthropic's audio models from research into production across Claude.ai, our mobile apps, and the Anthropic API. You'll work at the intersection of real-time media, low-latency inference, and distributed systems,building infrastructure where every millisecond of latency is felt by the user.

We partner closely with the Audio research team, who train the speech understanding and generation models, and with product teams shipping voice experiences to users. Your job is to make those models fast, reliable, and delightful to talk to at scale.

Responsibilities

• Design and build the real-time streaming infrastructure that powers voice conversations with Claude,ingesting microphone audio, orchestrating model inference, and streaming synthesized speech back with minimal latency

• Build low-latency serving systems for speech models, optimizing time-to-first-audio and end-to-end conversational responsiveness

• Develop the public and internal APIs that expose voice capabilities to Claude.ai, mobile clients, and third-party developers

• Own the audio transport layer,codecs, jitter buffers, adaptive bitrate, packet loss recovery,so conversations stay smooth across unreliable networks

• Build observability and quality-measurement systems for voice: latency distributions, audio quality metrics, interruption handling, and turn-taking accuracy

• Partner with Audio research to move new model architectures from experiment to production, and feed real-world performance data back into research

• Collaborate with mobile and product engineering on client-side audio capture, playback, and the end-to-end user experience

You may be a good fit if you

• Have 6+ years of experience building distributed systems, real-time infrastructure, or platform services at scale

• Have shipped production systems where latency is measured in tens of milliseconds and users notice when you miss

• Are comfortable working across the stack,from transport protocols and serving infrastructure up to the APIs product teams build on

• Are results-oriented, with a bias toward flexibility and impact

• Pick up slack, even if it goes outside your job description

• Enjoy pair programming (we love to pair!)

• Care about the societal impacts of voice AI and want to help shape how these systems are developed responsibly

• Are comfortable with ambiguity,voice is a fast-moving space, and you'll help define the architecture as we learn what works

Strong candidates may also have experience with

• Real-time media protocols and stacks: WebRTC, RTP, gRPC bidirectional streaming, or WebSockets at scale

• Audio engineering fundamentals: codecs (Opus, AAC), voice activity detection, echo cancellation, jitter buffering, or audio DSP

• Low-latency ML inference serving, streaming model outputs, or GPU-based serving infrastructure

• Telephony, live streaming, video conferencing, or voice assistant platforms

• Mobile audio pipelines on iOS (AVAudioEngine, AudioUnits) or Android (Oboe, AAudio)

• Working alongside ML researchers to productionize models,speech experience is a plus but not required

Representative projects

• Driving time-to-first-audio below human perceptual thresholds by co-designing the serving pipeline with the Audio research team

• Building a streaming inference orchestrator that interleaves speech recognition, LLM reasoning, and speech synthesis with overlapping execution

• Designing the voice mode API surface for the Anthropic API so developers can build their own voice agents on Claude

• Implementing graceful barge-in and interruption handling so users can cut Claude off mid-sentence naturally

• Instrumenting end-to-end audio quality metrics and building dashboards that catch regressions before users do

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The Voice Platform team designs and operates the serving systems, streaming pipelines, and APIs that bring Anthropic's audio models from research into production across Claude.ai, our mobile apps, and the Anthropic API. You'll work at the intersection of real-time media, low-latency inference, and distributed systems,building infrastructure where every millisecond of latency is felt by the user.

We partner closely with the Audio research team, who train the speech understanding and generation models, and with product teams shipping voice experiences to users. Your job is to make those models fast, reliable, and delightful to talk to at scale.

Responsibilities:

• Design and build the real-time streaming infrastructure that powers voice conversations with Claude,ingesting microphone audio, orchestrating model inference, and streaming synthesized speech back with minimal latency

• Build low-latency serving systems for speech models, optimizing time-to-first-audio and end-to-end conversational responsiveness

• Develop the public and internal APIs that expose voice capabilities to Claude.ai, mobile clients, and third-party developers

• Own the audio transport layer,codecs, jitter buffers, adaptive bitrate, packet loss recovery,so conversations stay smooth across unreliable networks

• Build observability and quality-measurement systems for voice: latency distributions, audio quality metrics, interruption handling, and turn-taking accuracy

• Partner with Audio research to move new model architectures from experiment to production, and feed real-world performance data back into research

• Collaborate with mobile and product engineering on client-side audio capture, playback, and the end-to-end user experience

You may be a good fit if you

• Have 6+ years of experience building distributed systems, real-time infrastructure, or platform services at scale

• Have shipped production systems where latency is measured in tens of milliseconds and users notice when you miss

• Are comfortable working across the stack,from transport protocols and serving infrastructure up to the APIs product teams build on

• Are results-oriented, with a bias toward flexibility and impact

• Pick up slack, even if it goes outside your job description

• Enjoy pair programming (we love to pair!)

• Care about the societal impacts of voice AI and want to help shape how these systems are developed responsibly

• Are comfortable with ambiguity,voice is a fast-moving space, and you'll help define the architecture as we learn what works

Strong candidates may also have experience with

• Real-time media protocols and stacks: WebRTC, RTP, gRPC bidirectional streaming, or WebSockets at scale

• Audio engineering fundamentals: codecs (Opus, AAC), voice activity detection, echo cancellation, jitter buffering, or audio DSP

• Low-latency ML inference serving, streaming model outputs, or GPU-based serving infrastructure

• Telephony, live streaming, video conferencing, or voice assistant platforms

• Mobile audio pipelines on iOS (AVAudioEngine, AudioUnits) or Android (Oboe, AAudio)

• Working alongside ML researchers to productionize models,speech experience is a plus but not required

Representative projects

• Driving time-to-first-audio below human perceptual thresholds by co-designing the serving pipeline with the Audio research team

• Building a streaming inference orchestrator that interleaves speech recognition, LLM reasoning, and speech synthesis with overlapping execution

• Designing the voice mode API surface for the Anthropic API so developers can build their own voice agents on Claude

• Implementing graceful barge-in and interruption handling so users can cut Claude off mid-sentence naturally

• Instrumenting end-to-end audio quality metrics and building dashboards that catch regressions before users do

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This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms. You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centres, including our primary front and backend networks that train Grok and that customers use for inference.

Responsibilities:

• Design, validate, and productise high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).
• Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterisation.
• Investigate the opportunity for LPO and LRO in our network.
• Evaluate early co-packaged and near-packaged engines for switches and GPUs.
• Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.
• Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.
• Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.
• Perform system-level simulation of end-to-end fabric performance.
• Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
• Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.

Basic Qualifications:

• At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacentre environment.
• Master's or PhD degree in Electrical Engineering, Photonics or Physics.
• Deep knowledge of PAM4 SerDes performance, equalisation, jitter, crosstalk.
• Solid operational understanding of FEC, Retimers, TIAs and Drivers.
• Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.
• Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterisation.
• Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.
• Knowledge of SiPh design process, yield improvement and reliability testing.
• Familiarity with CPO technologies and challenges/risk areas.
• Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.
• Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.

Compensation and Benefits:

$180,000 - $440,000 USD

Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.

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At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, powering self-driving cars, cloud infrastructure, and learning machines.

You Are:

A Staff-level analog/MS engineer who owns complex designs end-to-end, influences architecture, and mentors others. You balance performance, reliability, and schedule in advanced CMOS and communicate clearly across teams.

If you are excited by the prospect of shaping high-speed connectivity in AI, cloud, automotive, and beyond - and you seek to empower some of the world's most advanced systems - this role is your opportunity to make a meaningful impact.

What You'll Be Doing:

• Taking end-to-end ownership of critical analog and mixed-signal blocks in high-speed SERDES designs
• Making architectural and circuit-level tradeoffs to optimize power, performance, area, and reliability
• Defining, verifying, and documenting testbenches for rigorous pre-silicon validation
• Leading custom analog layout coordination, ensuring parasitic awareness and post-layout optimization
• Driving robustness and quality sign-off processes, including PVT, mismatch, aging, reliability, and yield analysis
• Aligning system-level interfaces and usability considerations for seamless integration
• Executing silicon bring-up, characterization, and correlation against design specifications
• Providing technical leadership, mentorship, and guidance within a collaborative, multidisciplinary team

What You'll Need:

• MS/PhD in Electronics/Computer Engineer or equivalent; typically 7+ years or equivalent Staff-level impact
• Deep analog/MS in deep sub-micron CMOS; signal integrity/noise/jitter
• Proven architecture tradeoffs and production silicon experience
• Strong custom analog layout collaboration; post-layout optimization
• Excellent communication; ability to influence across teams

The Team You'll Be A Part Of:

You will join the IP and System Solutions Group, a cornerstone of Synopsys' mission to enable the industry's most advanced silicon. The SERDES team is renowned for developing high-speed interface IP, deployed across a wide range of applications and technology nodes. This multidisciplinary group collaborates closely to deliver high-performance, power-efficient chips, optimizing power, performance, and area (PPA) while accelerating time-to-market. You'll work alongside experts in architecture, circuit design, layout, and system integration, fostering innovation and excellence in every project.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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