You are an accomplished analog design engineer with a passion for driving innovation in high-speed memory interface technologies. With 8-15 years of experience, you have mastered the fundamentals of analog design and device physics, and you thrive in environments that challenge you to push the boundaries of what is possible. Your expertise in high-speed IO designs, especially in advanced process technologies like CMOS, FinFET, and GAA, positions you as a technical leader. You are motivated by the opportunity to lead and mentor teams, guiding them to deliver best-in-class products that set industry benchmarks for performance and reliability.

You possess a deep understanding of JEDEC requirements and standards for memory interfaces, making you a trusted authority in the development of DDR, HBM, and UCIe PHY IPs. Your knowledge of ESD and reliability concepts ensures robust designs, while your familiarity with signal and power integrity further strengthens your technical arsenal. Communication is your forte; you articulate complex ideas clearly and collaborate effectively across global, cross-functional teams. You are as comfortable in technical discussions as you are in strategic planning, always advocating for quality and innovation.

You value inclusivity and thrive in a diverse, collaborative workspace. You are driven by curiosity, always seeking new solutions and technologies, and you approach challenges with resilience and adaptability. Your leadership inspires others to reach their full potential, and you are committed to continuous learning and professional growth.

You will lead the design and development of next-generation high-speed memory interface PHY IPs, including DDR, HBM, and UCIe. You will drive innovation in high-speed IO circuit designs for memory interfaces using advanced process technologies (CMOS, FinFET, GAA). You will collaborate with global cross-functional teams to deliver integrated solutions. You will apply analog design fundamentals and device physics expertise to optimize performance, power, and area of memory interface circuits. You will ensure compliance with JEDEC standards and requirements, contributing to industry-leading reliability and robustness.

You will mentor and guide design teams to achieve quality milestones, fostering a culture of technical excellence and continuous improvement. You will participate in design reviews, providing technical leadership and constructive feedback to peers and junior engineers. You will support product integration and validation, troubleshooting issues, and optimizing designs for manufacturability and scalability.

You will accelerate the development of cutting-edge memory interface solutions, advancing Synopsys' leadership in semiconductor IP. You will enable customers to build faster, more reliable, and energy-efficient silicon chips for applications ranging from AI to data centers. You will shape industry standards by ensuring compliance and contributing to the evolution of JEDEC and related protocols. You will drive technical innovation, introducing new architectures and methodologies that transform high-speed IO design.

You will mentor and elevate the capabilities of the engineering team, fostering a collaborative and high-performance culture. You will deliver robust products with exceptional signal and power integrity, setting benchmarks for quality and reliability. You will strengthen Synopsys' reputation as the go-to provider for advanced memory interface IPs. You will contribute to the global engineering community through technical presentations, publications, and cross-team knowledge sharing.

XML job scraping automation by YubHub