Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nAs a Staff Engineer in our ASIC Digital Design team, you will be responsible for leading and driving ownership of critical areas of verification alongside a team of talented verification engineers. You will define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for Subsystem.
\nYour responsibilities will include specifying, building, enhancing, and maintaining state-of-the-art Subsystem top-level UVM-based System Verilog testbenches, integrating RTL and behavioral models. You will also code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
\nIn addition, you will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met. You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.
\nYou will work closely with RTL designers and architects to ensure functional correctness and collaborate with a global team of experienced verification engineers, fostering knowledge sharing and professional growth.
\nAs a Staff Engineer, you will have the opportunity to make a significant impact on the success of our Subsystem and contribute to the early detection and resolution of critical design issues, reducing time-to-market and silicon re-spins.
\nYou will also enhance Synopsys' reputation as the premier provider of high-speed connectivity IP Subsystem through engineering excellence and innovation, and bolster Synopsys' leadership in chip design by ensuring our IP verification methodologies set industry standards.
\nXML job scraping automation by YubHub
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\nWe are seeking a senior verification leader to drive the strategy, execution, and quality of next-generation PCIe PHY IP verification. As a Principal Engineer, you will define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs.
\nKey Responsibilities:
\nImpact:
\nRequirements:
\nTeam:
\nYou'll join a world-class group of engineers dedicated to advancing high-speed silicon IP solutions. Our team specializes in PCIe PHY technology, collaborating across design, analog, firmware, architecture, and validation disciplines to deliver IP products that set industry benchmarks for performance, power efficiency, and reliability.
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
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