{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/ip-integration"},"x-facet":{"type":"skill","slug":"ip-integration","display":"Ip Integration","count":8},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8142c2c7-bfb"},"title":"Principal STA Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Principal STA Engineer, you will be responsible for owning full-chip and block-level STA sign-off across all PVT corners and operational modes. You will drive timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Owning full-chip and block-level STA sign-off across all PVT corners and operational modes.</li>\n<li>Driving timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.</li>\n<li>Analyzing and resolving setup/hold violations, noise, signal integrity (SI), OCV, and derates.</li>\n<li>Defining and validating timing margins, guard-bands, and sign-off criteria for advanced node designs.</li>\n<li>Managing complexities at 7nm, 5nm, and 3nm nodes, including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution.</li>\n<li>Developing and reviewing SDC constraints (clocks, IO delays, exceptions) for MCMM designs.</li>\n<li>Building scalable timing methodologies and driving constraint validation and consistency across teams.</li>\n<li>Utilizing STA tools (Primetime, Tempus) and scripting (Tcl/Python) for automation and flow efficiency.</li>\n<li>Leading timing reviews and sign-off meetings with cross-functional stakeholders.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Ensuring successful tapeouts and robust silicon performance at advanced technology nodes.</li>\n<li>Driving innovation in timing sign-off methodologies, influencing industry standards and best practices.</li>\n<li>Reducing time-to-market by achieving efficient timing closure and minimizing design iterations.</li>\n<li>Enhancing cross-functional collaboration and knowledge sharing within Synopsys engineering teams.</li>\n<li>Mentoring and developing junior engineers, building a stronger and more resilient team.</li>\n<li>Contributing to architectural decisions that improve timing convergence and silicon reliability.</li>\n<li>Streamlining timing analysis workflows through automation, improving productivity and accuracy.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>B.Eng, or MS in Electrical Engineering or a related field.</li>\n<li>10–15+ years of experience in STA and timing sign-off for SoCs.</li>\n<li>Proven record of successful tapeouts in advanced nodes (7nm, 5nm, 3nm).</li>\n<li>Expertise in STA tools (Primetime, Tempus) and scripting languages (Tcl, Python, Perl).</li>\n<li>Deep understanding of EM/IR and reliability impacts on timing.</li>\n<li>Experience with full-chip integration and hierarchical STA methodologies.</li>\n<li>Ability to develop scalable timing methodologies for MCMM designs.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Technical leader and mentor, passionate about knowledge sharing.</li>\n<li>Collaborative communicator, able to lead cross-functional teams and drive consensus.</li>\n<li>Detail-oriented and analytical, with a relentless focus on quality and accuracy.</li>\n<li>Innovative thinker, eager to explore new approaches and technologies.</li>\n<li>Adaptable, capable of navigating fast-paced and evolving engineering environments.</li>\n<li>Confident decision-maker, able to advocate for best practices and influence architectural choices.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join a dynamic, highly skilled SOC engineering team dedicated to delivering world-class silicon solutions at the forefront of semiconductor technology.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8142c2c7-bfb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/austin/principal-sta-engineer/44408/93189758160","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$170,000-$255,000","x-skills-required":["STA","timing sign-off","SoCs","Primetime","Tempus","Tcl","Python","Perl","EM/IR","reliability impacts on timing","full-chip integration","hierarchical STA methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:05.689Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"STA, timing sign-off, SoCs, Primetime, Tempus, Tcl, Python, Perl, EM/IR, reliability impacts on timing, full-chip integration, hierarchical STA methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":170000,"maxValue":255000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_3f49e55b-9eb"},"title":"Sales Account Management, Sr Staff","description":"<p>Engineer the Future with Us</p>\n<p>We currently have 614 open roles</p>\n<p><strong>Innovation Starts Here</strong></p>\n<p>Find Jobs For</p>\n<p>Where?When autocomplete results are available use up and down arrows to review and enter to select. Touch device users, explore by touch or with swipe gestures.</p>\n<p><strong>Sales Account Management, Sr Staff - HiTech</strong></p>\n<p>Shanghai, Shanghai Municipality, China</p>\n<p>Save</p>\n<p>Category: SalesHire Type: Employee</p>\n<p><strong>Job ID</strong> 16465<strong>Date posted</strong> 03/22/2026</p>\n<p><strong><strong>We Are:</strong></strong></p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong><strong>You Are:</strong></strong></p>\n<p>You are a seasoned sales professional with a passion for connecting technology solutions to customer needs. You thrive in dynamic environments, leveraging your deep understanding of the semiconductor industry to build meaningful relationships and drive business growth. You possess a strategic mindset, consistently identifying opportunities to expand market share and deliver value to clients. Your high energy and collaborative spirit make you a trusted partner both internally and externally. You are adept at navigating complex sales cycles, communicating technical concepts to varied audiences, and negotiating win-win outcomes. Comfortable with ambiguity, you proactively seek solutions, adapt to evolving priorities, and inspire your team to achieve ambitious goals. You value diversity and inclusion, recognizing the power of varied perspectives in delivering exceptional results. Your commitment to excellence is evident in your meticulous attention to detail, relentless pursuit of targets, and dedication to continuous learning. You are motivated not only by individual success but by contributing to the broader mission of Synopsys, helping to shape the future of technology in Shanghai and beyond.</p>\n<p><strong><strong>What You’ll Be Doing:</strong></strong></p>\n<ul>\n<li>Developing and executing strategic account plans for key customers in the semiconductor, electronics, and software sectors.</li>\n</ul>\n<ul>\n<li>Building and maintaining long-term relationships with clients, ensuring high levels of satisfaction and retention.</li>\n</ul>\n<ul>\n<li>Identifying new business opportunities, driving revenue growth through solution-based selling.</li>\n</ul>\n<ul>\n<li>Collaborating closely with technical teams to align Synopsys’ offerings with customer requirements and market trends.</li>\n</ul>\n<ul>\n<li>Managing complex sales cycles, including contract negotiations, pricing discussions, and closing deals.</li>\n</ul>\n<ul>\n<li>Providing market insights and feedback to internal stakeholders to inform product development and business strategy.</li>\n</ul>\n<ul>\n<li>Representing Synopsys at industry events, conferences, and customer meetings to showcase our innovative solutions.</li>\n</ul>\n<p><strong><strong>The Impact You Will Have:</strong></strong></p>\n<ul>\n<li>Drive significant revenue growth across the Greater China region, contributing to Synopsys’ global expansion.</li>\n</ul>\n<ul>\n<li>Strengthen Synopsys’ market position by developing deep customer relationships and identifying strategic opportunities.</li>\n</ul>\n<ul>\n<li>Influence product direction by bringing customer feedback and market intelligence to internal teams.</li>\n</ul>\n<ul>\n<li>Enhance customer satisfaction by delivering tailored solutions and exceptional service.</li>\n</ul>\n<ul>\n<li>Foster cross-functional collaboration between sales, engineering, and marketing teams.</li>\n</ul>\n<ul>\n<li>Champion Synopsys’ brand and technology leadership within the industry.</li>\n</ul>\n<p><strong><strong>What You’ll Need:</strong></strong></p>\n<ul>\n<li>Bachelor’s degree in Engineering, Business, or related field; Master’s preferred.</li>\n</ul>\n<ul>\n<li>8+ years of sales experience, preferably within semiconductor, EDA, or high-tech industries.</li>\n</ul>\n<ul>\n<li>Proven track record of exceeding sales targets and managing enterprise-level accounts.</li>\n</ul>\n<ul>\n<li>Strong understanding of chip design, verification, and IP integration technologies.</li>\n</ul>\n<ul>\n<li>Exceptional negotiation, communication, and presentation skills.</li>\n</ul>\n<ul>\n<li>Familiarity with CRM tools and sales analytics platforms.</li>\n</ul>\n<p><strong><strong>Who You Are:</strong></strong></p>\n<ul>\n<li>Strategic thinker with a results-driven mindset.</li>\n</ul>\n<ul>\n<li>Excellent problem-solving and analytical abilities.</li>\n</ul>\n<ul>\n<li>Collaborative team player who values diverse perspectives.</li>\n</ul>\n<ul>\n<li>Adaptable, resilient, and proactive in facing challenges.</li>\n</ul>\n<ul>\n<li>Customer-centric with strong relationship-building skills.</li>\n</ul>\n<ul>\n<li>Ethical, trustworthy, and committed to delivering value.</li>\n</ul>\n<p><strong><strong>The Team You’ll Be A Part Of:</strong></strong></p>\n<p>You’ll join a dynamic and highly skilled sales team focused on driving growth in Shanghai and the broader Greater China region. Our team collaborates closely with technical experts, marketing professionals, and global leadership to deliver innovative solutions tailored to customer needs. We foster a culture of support, knowledge sharing, and continuous improvement, empowering each member to achieve their full potential.</p>\n<p><strong><strong>Rewards and Benefits:</strong></strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_3f49e55b-9eb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/shanghai/sales-account-management-sr-staff-hitech/44408/93110948944","x-work-arrangement":null,"x-experience-level":"senior","x-job-type":"employee","x-salary-range":null,"x-skills-required":["chip design","verification","IP integration","CRM tools","sales analytics platforms"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:54.382Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Shanghai"}},"occupationalCategory":"sales","industry":"technology","skills":"chip design, verification, IP integration, CRM tools, sales analytics platforms"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f59277e9-bc1"},"title":"Senior Product Sales Manager (Embedded Systems)","description":"<p>Join Synopsys to transform the future through continuous technological innovation.</p>\n<p>As a Senior Product Sales Manager (Embedded Systems), you will be responsible for driving product sales activities for new and renewal business across assigned product lines to achieve or exceed revenue objectives.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Selling products and services through both telephone and face-to-face interactions, adapting your approach to suit customer preferences.</li>\n<li>Collaborating with field sales, enterprise sales, and channel partners to develop and execute strategies that maximize product and service revenue.</li>\n<li>Identifying and uncovering opportunities in current and new accounts, seamlessly transitioning leads to direct sales teams for follow-up.</li>\n<li>Facilitating communication between sales and technical teams to share updates on product capabilities, success stories, and winning strategies.</li>\n</ul>\n<p>In this role, you will have the opportunity to:</p>\n<ul>\n<li>Accelerate revenue growth and market share for assigned product lines through proactive sales and strategic partnerships.</li>\n<li>Enhance the visibility and reputation of Synopsys solutions within the industry by delivering impactful presentations and participating in conventions.</li>\n<li>Strengthen relationships with customers and partners, fostering loyalty and long-term engagement.</li>\n</ul>\n<p>To succeed in this role, you will need:</p>\n<ul>\n<li>A bachelor&#39;s degree in technical, engineering, business, or related field; or equivalent sales/consulting experience.</li>\n<li>Minimum 4+ years of sales or consulting experience in engineering/technology applications with proven success, or 6+ years without a degree.</li>\n<li>Strong understanding of product market position and sales fundamentals.</li>\n<li>Ability to work cross-functionally with teams such as ACE, DEV, Marketing, PM, and across various hierarchies.</li>\n<li>Proven ability to foster collaboration and coordinate with globally distributed personnel.</li>\n<li>Aptitude for problem-solving and delivering tailored solutions for customers.</li>\n<li>Fluency in English and the local language of the territory.</li>\n<li>Willingness and ability to travel up to 50% as required.</li>\n</ul>\n<p>If you are a driven and results-oriented sales professional with a passion for technology and engineering solutions, we encourage you to apply for this exciting opportunity.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f59277e9-bc1","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/novi/senior-product-sales-manager-embedded-systems/44408/92736415824","x-work-arrangement":"remote","x-experience-level":"senior","x-job-type":"employee","x-salary-range":"$126,000-$189,000","x-skills-required":["Sales","Product Management","Technical Sales","Engineering","Problem-Solving","Communication","Collaboration","Global Travel"],"x-skills-preferred":["Embedded Systems","Chip Design","Verification","IP Integration","Electronic Design Automation","Intellectual Property"],"datePosted":"2026-04-05T13:21:39.826Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"United States"}},"jobLocationType":"TELECOMMUTE","occupationalCategory":"Sales","industry":"Technology","skills":"Sales, Product Management, Technical Sales, Engineering, Problem-Solving, Communication, Collaboration, Global Travel, Embedded Systems, Chip Design, Verification, IP Integration, Electronic Design Automation, Intellectual Property","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":126000,"maxValue":189000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5be91f86-bf9"},"title":"ASIC Physical Design, Sr Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.</p>\n<p>They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).</p>\n<p>You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.</p>\n<p>You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.</p>\n<p>You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.</p>\n<p>You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.</p>\n<p>You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.</p>\n<p>You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.</p>\n<p>You will mentor junior engineers and contribute to team knowledge sharing initiatives.</p>\n<p><strong>Impact</strong></p>\n<p>You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.</p>\n<p>You will advance Synopsys&#39; leadership in IP implementation at cutting-edge technology nodes.</p>\n<p>You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.</p>\n<p>You will facilitate seamless cross-site collaboration, ensuring global project success.</p>\n<p>You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.</p>\n<p>You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.</p>\n<p><strong>Requirements</strong></p>\n<p>Bachelor&#39;s or Master&#39;s degree in Electronics, Electrical Engineering, or related field.</p>\n<p>3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).</p>\n<p>Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).</p>\n<p>Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.</p>\n<p>Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.</p>\n<p>Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.</p>\n<p>Strong analytical and debugging skills for addressing complex design challenges.</p>\n<p><strong>Team</strong></p>\n<p>You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.</p>\n<p>The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.</p>\n<p>Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_5be91f86-bf9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IP implementation","Timing closure","Clock tree synthesis","Skew balancing","Mixed-signal IP integration","Scripting languages (Tcl, Perl, Python)","Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:24.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IP implementation, Timing closure, Clock tree synthesis, Skew balancing, Mixed-signal IP integration, Scripting languages (Tcl, Perl, Python), Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1760e65e-8ff"},"title":"Applications Engineering Architect (PPA)","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a proactive, results-driven leader with a deep technical background in physical design and processor implementation. Your expertise is grounded in architecting high-performance, energy-efficient silicon solutions, and you thrive in fast-paced, collaborative environments. You possess a strong sense of ownership and are comfortable navigating ambiguity to deliver innovative solutions to complex engineering challenges.</p>\n<p>As an Applications Engineering Architect (PPA), you will be responsible for architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems, targeting aggressive power and performance goals for diverse end-user applications. You will develop and refine advanced EDA tools and design methodologies to support state-of-the-art processor implementations.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Architecting and executing the physical design of high-performance, energy-efficient processors and processor-based subsystems</li>\n<li>Developing and refining advanced EDA tools and design methodologies</li>\n<li>Collaborating closely with key Synopsys customers to guide their development of processor-based platforms in advanced silicon technologies</li>\n<li>Partnering with Synopsys R&amp;D and marketing teams to influence and define future product roadmaps and features</li>\n<li>Working in synergy with leading IP partners to ensure seamless integration of EDA tools, methodologies, and IP</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Proven expertise in physical design and implementation of high-performance processors, SoCs, or processor-based subsystems</li>\n<li>In-depth experience with advanced EDA tools, flows, and methodologies for digital implementation</li>\n<li>Strong knowledge of silicon technologies at advanced nodes and associated design challenges</li>\n<li>Hands-on experience integrating IP and collaborating with IP vendors for seamless tool and methodology interoperability</li>\n<li>Track record of working directly with customers, understanding their requirements, and delivering tailored solutions</li>\n</ul>\n<p>We offer a comprehensive range of health, wellness, and financial benefits, including medical, dental, and vision insurance, 401(k) matching, and paid time off. We also provide opportunities for professional growth and development, including training and education programs, mentorship, and career advancement opportunities.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1760e65e-8ff","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/applications-engineering-architect-ppa/44408/92048243568","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","processor implementation","EDA tools","digital implementation","silicon technologies","IP integration"],"x-skills-preferred":["Python","Tcl","Perl","power/performance/area trade-offs","optimization techniques"],"datePosted":"2026-03-09T11:06:19.000Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru, Karnataka, India"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, processor implementation, EDA tools, digital implementation, silicon technologies, IP integration, Python, Tcl, Perl, power/performance/area trade-offs, optimization techniques"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_84c32509-79a"},"title":"ASIC Physical Design, Principal Engineer","description":"<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a visionary and seasoned engineering leader, driven by a passion for innovation in ASIC physical design. Seeking a highly motivated and innovative ASIC Physical Design Implementation Engineer to lead the Test Chip PHY development. You will lead a team of engineers to develop Test Chips for DDR/HBM/UCIe protocols. The position offers an excellent opportunity to work on mixed-signal IPs with a focus on digital design.</p>\n<p>What You’ll Be Doing:</p>\n<p>Lead Test Chip Physical Design Implementation: Oversee all aspects of physical implementation for test chips, including integration of IP blocks and custom logic for validation purposes. Candidate will lead multiple test chips that will be developed in parallel to tape-out for various foundry shuttles.</p>\n<p>Resource &amp; Project Leadership: Lead a team of physical design engineers; allocate resources, schedule tasks, and manage priorities for on-time project execution.</p>\n<p>Floor planning &amp; Power Planning: Develop overall floorplan and power/ground strategy tailored for the test chip architecture.</p>\n<p>Synthesis to GDSII: Own and drive the entire RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</p>\n<p>Timing Closure: Execute and oversee static timing analysis (STA) for the test chip, ensuring robust timing signoff.</p>\n<p>Design Integrity Checks: Conduct and resolve EM/IR drop analysis and physical verification (ERC/DRC/LVS), as well as PERC/ESD analysis specific to test chips.</p>\n<p>Block/Chip-level Integration: Integrate updated covercells, circuit/IP/PLL/hard-macros, abutment checking, and QA/review/release of hard-macros.</p>\n<p>Tool Flow Enhancements &amp; Debug: Drive tool flow automation and debugging to improve productivity and design reliability.</p>\n<p>Collaboration: Work closely with Architecture, FE RTL, Circuit and Covercell teams before and during the TC development</p>\n<p>Release &amp; Documentation: Prepare and release all supporting views necessary for the tape out of the test chips on to the foundry portal. File, update and maintain the mask tooling form on the foundry website and fill out the necessary checklists</p>\n<p>What You’ll Need:</p>\n<ul>\n<li>12+ years of proven experience in ASIC physical Design, with expertise in leading complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep knowledge of the entire ASIC physical design flow, including floor planning, synthesis, place and route, timing closure, IR-drop/EM analysis, LVS/DRC, and related methodologies.</li>\n<li>Demonstrated experience leading engineering teams and managing cross-functional projects in high-pressure environments.</li>\n<li>Familiarity with test chip methodology, IP integration, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as DC, PT, ICC2/FC, ICV, Calibre, RedHawk, and advanced technologies like FinFet.</li>\n<li>Strong communication, problem-solving, and project management skills.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Elevate Synopsys’ leadership in advanced ASIC and IP development by delivering high-performance, reliable test chips.</li>\n<li>Enable rapid validation and integration of DDR/HBM/UCIe protocols, supporting next-generation silicon innovation.</li>\n<li>Enhance cross-functional collaboration, accelerating project timelines and improving overall design quality.</li>\n<li>Drive process improvements through tool flow automation, setting new standards for productivity and design reliability.</li>\n<li>Ensure robust manufacturability and performance, reducing risk and increasing success rates in foundry tape-outs.</li>\n<li>Mentor and develop junior engineers, fostering a culture of technical excellence and continuous learning.</li>\n<li>Contribute to the creation of industry-leading mixed-signal IPs, elevating Synopsys’ portfolio and market position.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Innovative thinker with a passion for solving complex engineering challenges.</li>\n<li>Inspirational leader who empowers teams and fosters collaborative, inclusive environments.</li>\n<li>Meticulous and detail-oriented, committed to quality and design integrity.</li>\n<li>Adaptable and resilient, thriving in fast-paced, dynamic settings.</li>\n<li>Excellent communicator, able to articulate technical concepts to diverse audiences.</li>\n<li>Continuous learner, eager to stay at the forefront of technology and industry trends.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a highly skilled, multidisciplinary team focused on developing industry-leading test chips for cutting-edge protocols like DDR, HBM, and UCIe. The team values collaboration, innovation, and technical excellence, working closely with architecture, RTL, circuit, and verification experts to deliver best-in-class mixed-signal IP solutions. Together, you’ll shape the next generation of silicon technology and drive Synopsys’ continued success in the semiconductor industry.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p>#LI-NK4</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.</p>\n<p>Back to nav</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>### Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>### Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>### Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>### ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>### Retirement Plans</li>\n</ul>\n<p>Save for your future with our 401(k) and 401(k) matching program.</p>\n<ul>\n<li>### Other Benefits</li>\n</ul>\n<p>Flexible work arrangements, employee discounts, and more.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_84c32509-79a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/boxborough/asic-physical-design-principal-engineer-15046/44408/91661594048","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$170,000-$255,000","x-skills-required":["ASIC physical design","CAD tools","FinFet","IP integration","test chip methodology","verification flows"],"x-skills-preferred":["leadership","project management","communication","problem-solving"],"datePosted":"2026-03-09T11:05:54.042Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Boxborough, Massachusetts"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, CAD tools, FinFet, IP integration, test chip methodology, verification flows, leadership, project management, communication, problem-solving","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":170000,"maxValue":255000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_88d376a4-992"},"title":"Sales Account Management, Staff","description":"<p>You are a dynamic and results-oriented sales professional with a passion for driving growth in high-tech environments. With a proven track record of building and nurturing strategic client relationships, you thrive in fast-paced, innovative settings.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Developing and executing strategic account plans to drive revenue growth and achieve sales targets.</li>\n<li>Building and maintaining strong relationships with key decision-makers at enterprise clients.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Extensive experience in enterprise sales within the semiconductor or technology industry.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_88d376a4-992","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/seongnam-si/sales-account-management-staff/44408/91568840288","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["extensive experience in enterprise sales within the semiconductor or technology industry","strong understanding of chip design, EDA tools, or IP integration solutions"],"x-skills-preferred":["strategic thinker with a solutions-oriented mindset","excellent collaborator who thrives in cross-functional teams"],"datePosted":"2026-02-11T16:06:33.549Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Seongnam-si, Gyeonggi-do, South Korea"}},"employmentType":"FULL_TIME","occupationalCategory":"Sales","industry":"Technology","skills":"extensive experience in enterprise sales within the semiconductor or technology industry, strong understanding of chip design, EDA tools, or IP integration solutions, strategic thinker with a solutions-oriented mindset, excellent collaborator who thrives in cross-functional teams"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_f66286eb-f5d"},"title":"Principal ASIC Design Engineer","description":"<p>We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Empowering the creation of high-performance silicon chips and software content.</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Strong technical skills in chip design, verification, and IP integration.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_f66286eb-f5d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/principal-engineer-asic-digital-design-die-to-die-communication-protocol/44408/88686757808","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["chip design","verification","IP integration"],"x-skills-preferred":["strong technical skills"],"datePosted":"2025-12-22T12:02:50.387Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida/Pune"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"chip design, verification, IP integration, strong technical skills"}]}