At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
\nWe are seeking a Staff Engineer (Virtual Prototyping) to join our team in Moreira, Porto, Portugal. As a Staff Engineer, you will be responsible for developing and delivering high-performance simulation models for automotive, enterprise, telecommunications, and cloud platforms. You will also configure and bring up complex software stacks and drivers on simulated hardware platforms, collaborate with other development teams, IP owners, third-party suppliers, support engineers, and customers to identify, implement, and deliver solutions.
\nKey Responsibilities:
\nImpact:
\nRequirements:
\nWho You Are:
\nRewards and Benefits:
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_2a648d1c-583","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/moreira/staff-engineer-virtual-prototyping/44408/92616533056","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["C","C++","Linux OS","IP implementation","driver development","Virtio","MIPI","Security","DMA","SSI","I2C","Mobile Storage","open-source build systems","Buildroot","Yocto","FFmpeg","GStreamer","OpenSSL","Python","SystemC","transaction-level modelling","TLM","embedded software development","Arm cores","Arm architecture","debugging","root-cause analysis"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:23:03.491Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Moreira"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"C, C++, Linux OS, IP implementation, driver development, Virtio, MIPI, Security, DMA, SSI, I2C, Mobile Storage, open-source build systems, Buildroot, Yocto, FFmpeg, GStreamer, OpenSSL, Python, SystemC, transaction-level modelling, TLM, embedded software development, Arm cores, Arm architecture, debugging, root-cause analysis"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_5be91f86-bf9"},"title":"ASIC Physical Design, Sr Engineer","description":"Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.
\nThey work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nAs a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).
\nYou will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.
\nYou will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.
\nYou will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.
\nYou will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.
\nYou will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.
\nYou will support the implementation of best practices in floorplanning, placement, routing, and power optimization.
\nYou will mentor junior engineers and contribute to team knowledge sharing initiatives.
\nImpact
\nYou will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.
\nYou will advance Synopsys' leadership in IP implementation at cutting-edge technology nodes.
\nYou will champion best-in-class timing closure and integration practices, raising the bar for design excellence.
\nYou will facilitate seamless cross-site collaboration, ensuring global project success.
\nYou will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.
\nYou will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.
\nRequirements
\nBachelor's or Master's degree in Electronics, Electrical Engineering, or related field.
\n3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).
\nProficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).
\nSolid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.
\nExperience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.
\nFamiliarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.
\nStrong analytical and debugging skills for addressing complex design challenges.
\nTeam
\nYou will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.
\nThe team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.
\nTogether, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nOur total rewards include both monetary and non-monetary offerings.
\nYour recruiter will provide more details about the salary range and benefits during the hiring process.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_5be91f86-bf9","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/asic-physical-design-sr-engineer/44408/92159183392","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR IP implementation","Timing closure","Clock tree synthesis","Skew balancing","Mixed-signal IP integration","Scripting languages (Tcl, Perl, Python)","Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:17:24.614Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR IP implementation, Timing closure, Clock tree synthesis, Skew balancing, Mixed-signal IP integration, Scripting languages (Tcl, Perl, Python), Physical design tools (Synopsys ICC2, PrimeTime, StarRC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cc644248-b48"},"title":"Physical Design Sr Staff Engineer - PnR","description":"Opening. This role exists to develop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.
\nWhat you'll do
\nDevelop and enhance PPA (Power, Performance, Area) methodologies for complex interface IPs at advanced technology nodes.
\nWhat you need
\nWhy this matters
\nShape the future of high-performance silicon by advancing methodologies that deliver superior PPA and TAT outcomes.
\nEnable Synopsys customers to achieve breakthrough performance and efficiency in their semiconductor products.
\nEnhance the predictability and simplicity of implementation processes for complex interface IPs.
\nAccelerate the adoption of next-generation design technologies and tools across the industry.
\nDrive innovation in low-power, high-performance design, influencing the direction of emerging semiconductor solutions.
\nEmpower Synopsys to remain at the forefront of chip design and IP integration through continuous improvement.
\nWhat you’ll need
\nWhy you’ll love this role
\nBenefits
\nAt Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.
\nXML job scraping automation by YubHub
","url":"https://yubhub.co/jobs/job_cc644248-b48","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/physical-design-sr-staff-engineer-pnr/44408/91653340960","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["physical design","high-performance and low-power methodologies","synthesis","timing closure","power optimization","constraints management","LEC","STA flows","advanced process nodes","complex IP implementation","scripting languages","RTL","DFT","LDRC","TCM","VCLP","PTPX","interface IP controllers"],"x-skills-preferred":["TCL","Perl","Python","UCie","PCIe","USB"],"datePosted":"2026-03-04T17:09:10.853Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"physical design, high-performance and low-power methodologies, synthesis, timing closure, power optimization, constraints management, LEC, STA flows, advanced process nodes, complex IP implementation, scripting languages, RTL, DFT, LDRC, TCM, VCLP, PTPX, interface IP controllers, TCL, Perl, Python, UCie, PCIe, USB"}]}