They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.

As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.

You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.

You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.

You will develop and implement advanced test plans and test environments at both unit and system levels.

You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.

You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.

This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.

You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.

You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.

You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.

You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.

You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.

You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.

You will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.

The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.

Collaboration, innovation, and a drive for excellence define our culture.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub