Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions.
\nThey work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.
\nThese engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nWe are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.
\nAs a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.
\nYou will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.
\nYou will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.
\nYou will develop and implement advanced test plans and test environments at both unit and system levels.
\nYou will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.
\nYou will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.
\nYou will manage regressions and contribute to the continuous improvement of verification strategies and test environments.
\nThis role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.
\nYou should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.
\nYou should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.
\nYou should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.
\nYou should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.
\nYou should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.
\nYou should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.
\nYou will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.
\nThe team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.
\nCollaboration, innovation, and a drive for excellence define our culture.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
\nOur total rewards include both monetary and non-monetary offerings.
\nYour recruiter will provide more details about the salary range and benefits during the hiring process.
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