{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/io-frame-requirements"},"x-facet":{"type":"skill","slug":"io-frame-requirements","display":"Io Frame Requirements","count":1},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_1a49fd5b-a39"},"title":"Layout Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills,both written and verbal,are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.</p>\n<p>Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards. Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting. Mentoring and guiding junior engineers, fostering growth and technical excellence within the team. Estimating project efforts, planning schedules, and executing projects in cross-functional settings. Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes. Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_1a49fd5b-a39","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93917039728","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","DDR and HBM PHY IPs","CMOS, FinFET, and GAA at 7nm and below","floorplanning","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","IO frame requirements"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:45.472Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, DDR and HBM PHY IPs, CMOS, FinFET, and GAA at 7nm and below, floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, IO frame requirements"}]}