{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/io-frame-and-pitch-requirements"},"x-facet":{"type":"skill","slug":"io-frame-and-pitch-requirements","display":"Io Frame And Pitch Requirements","count":3},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. 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Join us to transform the future through continuous technological innovation.</p>\n<p><strong>You Are:</strong> You are an experienced layout design engineer with a passion for technological advancement and an eye for detail. You thrive in collaborative, fast-paced environments and are motivated by the challenge of developing next-generation DDR and HBM PHY IPs. With over five years of hands-on experience in layout development, you are adept at navigating complex process technologies such as CMOS, FinFET, and GAA at 7nm and below. You are a natural leader, capable of mentoring junior engineers, driving project execution, and ensuring the highest standards of product quality. Your expertise spans floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO frame requirements. You understand the importance of customer requirements at the PHY level and are committed to delivering differentiated solutions that help customers meet their unique performance, power, and size targets. Your communication skills,both written and verbal,are exceptional, enabling you to foster accountability and ownership within cross-functional teams. Above all, you value inclusion, diversity, and continuous learning, and are eager to contribute to a workplace that celebrates innovative thinking and collaboration.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Leading the development of cutting-edge DDR and HBM layout IPs, setting technical direction and standards.</li>\n<li>Providing hands-on expertise in layout creation, problem-solving, and technical troubleshooting.</li>\n<li>Mentoring and guiding junior engineers, fostering growth and technical excellence within the team.</li>\n<li>Estimating project efforts, planning schedules, and executing projects in cross-functional settings.</li>\n<li>Collaborating with teams to support critical layout requirements, floorplanning, and quality assurance processes.</li>\n<li>Conducting layout reviews, ensuring compliance with release processes, and meeting stringent customer requirements.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate the integration of advanced silicon IP in SoCs, driving innovation in smart devices and systems.</li>\n<li>Enhance product differentiation and performance, enabling customers to meet demanding market requirements.</li>\n<li>Reduce time-to-market and risk for customers through robust layout design and technical leadership.</li>\n<li>Support Synopsys’ reputation as a leader in DDR &amp; HBM PHY IP development, contributing to industry benchmarks.</li>\n<li>Foster an inclusive and collaborative engineering culture that values accountability and technical excellence.</li>\n<li>Mentor and develop the next generation of layout engineers, ensuring sustained innovation and talent growth.</li>\n</ul>\n<p><strong>What You’ll Need:</strong></p>\n<ul>\n<li>BTech/MTech in Electronics, Electrical Engineering, or related field.</li>\n<li>5+ years of relevant experience in layout design, preferably in DDR &amp; HBM PHY IP development.</li>\n<li>Deep understanding of submicron effects, floorplan techniques in CMOS, FinFET, GAA technologies (7nm and below).</li>\n<li>Expertise in layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.</li>\n<li>Strong ability to lead projects, manage schedules, and ensure product quality within tight timelines.</li>\n<li>Excellent written, verbal communication, and interpersonal skills.</li>\n</ul>\n<p><strong>Who You Are:</strong></p>\n<ul>\n<li>Innovative thinker with a proactive approach to problem-solving.</li>\n<li>Effective communicator and collaborator across diverse teams.</li>\n<li>Detail-oriented, accountable, and committed to high standards of quality.</li>\n<li>Mentor and leader, fostering growth and technical excellence.</li>\n<li>Adaptable, eager to learn, and open to new ideas and technologies.</li>\n<li>Champion for inclusion, diversity, and teamwork.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of:</strong> You will join a dynamic Silicon IP team focused on developing high-performance DDR and HBM PHY IPs. Our team values technical innovation, collaborative problem-solving, and continuous improvement. We work closely with cross-functional groups including design, verification, and customer support to deliver industry-leading solutions that shape the future of smart technology.</p>\n<p><strong>Rewards and Benefits:</strong> We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_26310f57-d67","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-staff-engineer/44408/93917039712","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","DDR and HBM PHY IPs","CMOS, FinFET, and GAA technologies","floorplanning","layout matching","ESD, latch-up, PERC, EMIR, DFM","LEF generation","IO frame and pitch requirements"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:11:45.685Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, DDR and HBM PHY IPs, CMOS, FinFET, and GAA technologies, floorplanning, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, IO frame and pitch requirements"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_471316cf-932"},"title":"Analog Layout, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. 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You will work on hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n<p>You will also mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n<p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings will be another key responsibility.</p>\n<p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks will also be a part of your role.</p>\n<p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables will be your additional responsibility.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li><p>Lead the design and development of cutting-edge DDR/HBM PHY layout IPs for next-generation technologies.</p>\n</li>\n<li><p>Hands-on execution of layout development, ensuring precision and adherence to industry standards.</p>\n</li>\n<li><p>Mentor and support junior engineers, fostering technical growth and knowledge sharing within the team.</p>\n</li>\n<li><p>Estimating project efforts, planning schedules, and executing projects in cross-functional settings.</p>\n</li>\n<li><p>Collaborating with teams to support critical layout, floorplanning requirements, layout reviews, and quality checks.</p>\n</li>\n<li><p>Managing the release process, ensuring timely delivery and consistent quality of layout deliverables.</p>\n</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li><p>BTech/MTech degree in Electrical Engineering, Electronics, or related field.</p>\n</li>\n<li><p>5+ years of relevant experience in layout design for CMOS, FinFET, GAA process technologies (7nm and below).</p>\n</li>\n<li><p>Expertise in layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements.</p>\n</li>\n<li><p>Strong understanding of floorplan techniques and deep submicron effects.</p>\n</li>\n<li><p>Proven ability to lead projects and deliver best product quality within tight timelines.</p>\n</li>\n</ul>\n<p>Preferred Qualifications:</p>\n<ul>\n<li><p>Collaborative and team-oriented, with a commitment to inclusion and diversity.</p>\n</li>\n<li><p>Detail-oriented, with strong problem-solving and analytical skills.</p>\n</li>\n<li><p>Effective communicator, both written and verbal, with excellent interpersonal abilities.</p>\n</li>\n<li><p>Adaptable and eager to learn, embracing new technologies and methodologies.</p>\n</li>\n<li><p>Empathetic mentor, fostering accountability, ownership, and technical growth in others.</p>\n</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li><p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n</li>\n<li><p>In addition to company holidays, we have ETO and FTO Programs.</p>\n</li>\n<li><p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n</li>\n<li><p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n</li>\n<li><p>Save for your future with our retirement plans that vary by region and country.</p>\n</li>\n<li><p>Competitive salaries.</p>\n</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_471316cf-932","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/analog-layout-staff-engineer/44408/92693931728","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["layout design","CMOS","FinFET","GAA process technologies","layout matching techniques","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":["collaborative and team-oriented","detail-oriented","effective communicator","adaptable and eager to learn","empathetic mentor"],"datePosted":"2026-04-05T13:21:26.995Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, CMOS, FinFET, GAA process technologies, layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements, collaborative and team-oriented, detail-oriented, effective communicator, adaptable and eager to learn, empathetic mentor"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_41cabece-785"},"title":"Layout Design, Sr Supervisor","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You are a visionary leader and seasoned layout design professional, passionate about advancing the frontiers of semiconductor technology. With over eight years of hands-on experience, you thrive in dynamic environments where innovation and technical excellence are paramount.</p>\n<p>You possess a deep understanding of deep submicron effects, advanced floorplanning techniques, and process technologies like CMOS, FinFET, and GAA at 7nm and below. Your expertise extends to layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, and IO frame and pitch requirements.</p>\n<p>You are adept at leading multi-disciplinary teams, creating an environment of accountability, ownership, and growth, while mentoring junior engineers and empowering senior team members to excel.</p>\n<p>You value diversity and inclusion, fostering a culture where every voice is heard and respected. Your collaborative approach ensures seamless cross-functional coordination, and you have a knack for translating complex technical requirements into actionable project plans.</p>\n<p>Your communication skills,both written and verbal,enable you to engage effectively with stakeholders at all levels. You are motivated by the opportunity to contribute to high-impact projects, drive innovation in DDR/HBM PHY IP layout, and deliver differentiated products that shape the industry.</p>\n<p>If you are ready to lead, inspire, and make a lasting impact, Synopsys is the place for you.</p>\n<p>Leading the development of next-generation DDR/HBM IP layouts, driving technical innovation and quality excellence.</p>\n<p>Mentoring and managing a team of layout engineers, fostering growth and maximizing individual and team potential.</p>\n<p>Developing and maintaining project schedules, ensuring timely delivery while balancing technical and resource constraints.</p>\n<p>Collaborating cross-functionally with design, verification, and IP teams to align on project requirements and execution.</p>\n<p>Providing subject matter expertise in high-speed DDR/HBM IP layout, including floorplanning, layout reviews, and quality checks.</p>\n<p>Executing layout matching techniques, ESD, latch-up, PERC, EMIR, DFM, LEF generation, and IO requirement analysis.</p>\n<p>Supporting layout automation through scripting and tool enhancement, optimizing efficiency and productivity.</p>\n<p>Acting as an advisor to resolve project challenges and guide teams towards innovative solutions.</p>\n<p>Accelerating the integration of advanced capabilities into SoCs, helping customers achieve unique performance, power, and size targets.</p>\n<p>Reducing time-to-market and risk for differentiated products through robust layout design and technical leadership.</p>\n<p>Driving continuous improvement in layout methodologies and quality standards across cross-functional teams.</p>\n<p>Empowering your team to deliver high-performance DDR/HBM PHY IPs that set industry benchmarks.</p>\n<p>Fostering a collaborative, inclusive work environment that values innovation, accountability, and diversity.</p>\n<p>Contributing to Synopsys’ reputation as the provider of the world’s broadest portfolio of silicon IP.</p>\n<p>Shaping the future of chip design and verification technologies through your expertise and leadership.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_41cabece-785","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/layout-design-sr-supervisor/44408/93269033008","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["deep submicron effects","advanced floorplanning techniques","CMOS","FinFET","GAA","layout matching","ESD","latch-up","PERC","EMIR","DFM","LEF generation","bond-pad layout","IO frame and pitch requirements"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:21:15.106Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"deep submicron effects, advanced floorplanning techniques, CMOS, FinFET, GAA, layout matching, ESD, latch-up, PERC, EMIR, DFM, LEF generation, bond-pad layout, IO frame and pitch requirements"}]}