Your responsibilities will include:

• Building, mentoring, and leading a high-performing team of Electrical Manufacturing Engineers and Specialists
• Leveraging expertise in New Product Introduction (NPI) to seamlessly transition PCBA, harnessing, and integration from prototype to high-volume production
• Being a strong partner with Product Quality Engineering to drive and support RCCA burndowns that tackle key issues both internally and externally to EW Production
• Collaborating with Design Engineering teams early in the development process to feedback Design For Manufacturability
• Defining workflows with cross-functional teams for effective collaboration

You will be responsible for owning a portion or all of the manufacturing value chain for a certain product or set of products. This includes developing process flows, breaking down large, complex assemblies into a logical part flow of subassemblies and sub-processes.

In addition, you will contribute to end-customer hardware mechanical or electrical design, including interconnects, board fabrication and inspection, etc.

As a Lead Manufacturing Engineer, you will have a degree in a technical field, such as engineering, math, or a hard science, and 8+ years of experience in a relevant field, preferably manufacturing or design of avionics or electrical systems.

You will have demonstrated ability to creatively deliver avionics hardware in a resource-constrained environment, and have in-kind or direct team leadership skills, with backing examples.

You will also have an attitude of world-class mission assurance, quality, attention to detail, and dedication, and a genuine interest in manufacturing and thirst for learning.

Preferred qualifications include experience with Avionics or Propulsion Products that require system AI&T (assembly, integration, and test), hands-on experience with software & firmware flashing or end-of-line testing & troubleshooting, and demonstrated success in scaling product testing and production from tens/hundreds to hundreds/thousands.

The salary range for this role is $146,000-$194,000 USD.

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The ideal candidate will have a degree in a technical field such as engineering, math, or a hard science, and 2+ years of experience in a relevant field, preferably manufacturing or design of electromechanical hardware. They will also have demonstrated ability to creatively deliver electromechanical hardware in a resource-constrained environment, and demonstrated in-kind or direct team leadership skills.

As a Lead Manufacturing Test Engineer, you will contribute to end-customer hardware mechanical or electrical design, including interconnects, board fabrication and inspection, etc. You will also travel to suppliers to do initial sourcing work, solve ongoing production issues, and implement quality procedures.

If you're a motivated and experienced engineer looking for a challenging role, we encourage you to apply.

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This strategic role will drive innovation in high-bandwidth, low-latency, power-efficient interconnects critical for AI/ML clusters based on advanced computing platforms. You will have the opportunity to work on all modalities of interconnects connecting GPUs and switches both inside and between data centres, including our primary front and backend networks that train Grok and that customers use for inference.

Responsibilities:

• Design, validate, and productise high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).
• Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterisation.
• Investigate the opportunity for LPO and LRO in our network.
• Evaluate early co-packaged and near-packaged engines for switches and GPUs.
• Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.
• Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.
• Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.
• Perform system-level simulation of end-to-end fabric performance.
• Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
• Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.

Basic Qualifications:

• At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacentre environment.
• Master's or PhD degree in Electrical Engineering, Photonics or Physics.
• Deep knowledge of PAM4 SerDes performance, equalisation, jitter, crosstalk.
• Solid operational understanding of FEC, Retimers, TIAs and Drivers.
• Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.
• Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterisation.
• Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.
• Knowledge of SiPh design process, yield improvement and reliability testing.
• Familiarity with CPO technologies and challenges/risk areas.
• Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.
• Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.

Compensation and Benefits:

$180,000 - $440,000 USD

Base salary is just one part of our total rewards package at X, which also includes equity, comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, and various other discounts and perks.

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You are an accomplished engineering leader with more than a decade of hands-on experience in SoC verification, emulation, and system-level validation. You thrive at the intersection of advanced hardware-assisted verification (HAV) and simulation acceleration (SimXL), bringing a deep understanding of complex SoC architectures, memory subsystems, and high-speed interconnects.

Architecting and leading Hardware-Assisted Verification and Simulation Acceleration solutions for large-scale SoCs and multi-die systems.

Driving end-to-end SimXL deployments, including use-case definition, performance optimization, and methodology standardization.

Defining and owning system-level verification and acceleration strategies spanning simulation, emulation, and prototyping.

Bridging gaps between RTL simulation, emulation, and software bring-up to enable early and scalable system validation.

Leading complex customer engagements involving HAV platforms, simulation acceleration, and hybrid verification flows.

Translating customer verification challenges into scalable, reusable solution architectures and acting as a technical authority in escalations.

Driving innovation in HAV and SimXL methodologies, including automation, reuse, and productivity frameworks leveraging AI/GenAI-assisted approaches.

Collaborating with R&D, Product Management, and Applications teams to influence product roadmaps and feature requirements.

Accelerate customer verification cycles, enabling earlier software and system bring-up for complex SoC designs.

Define and scale best-in-class HAV and SimXL solutions across strategic accounts, enhancing customer outcomes.

Drive measurable improvements in performance, capacity, and debug productivity for verification workflows.

Shape the future of AI-assisted verification and solution deployment within Synopsys and across the industry.

Act as a key technical leader in advancing the organization’s verification acceleration strategy.

Mentor and empower senior engineers, fostering a culture of innovation and technical excellence.

Influence product direction and solution roadmaps through deep technical insights and customer engagement.

10+ years of experience in SoC verification, emulation, or system-level validation.

Deep hands-on expertise in Hardware-Assisted Verification, simulation acceleration, and hybrid verification flows.

Strong experience with emulation platforms and accelerated simulation environments.

Solid understanding of SoC architectures, interconnects, memory subsystems, and software bring-up challenges.

Proven ability to design and deploy scalable verification solutions for complex designs.

Experience with system-level testbenches, transactors, and acceleration frameworks.

Exposure to GenAI or AI-assisted techniques applied to verification, debug, or solution automation.

Background in high-speed interfaces, memory subsystems, or multi-die architectures.

Track record of creating reusable assets, methodologies, or automation frameworks.

Experience influencing product direction or defining solution roadmaps.

Innovative thinker with a passion for driving technological advancement and automation.

Collaborative leader who mentors and inspires teams across geographies.

Strong communicator adept at translating complex technical concepts for diverse audiences.

Customer-focused problem solver with a commitment to delivering impactful solutions.

Adaptable and resilient in fast-paced, matrixed environments.

Detail-oriented, analytical, and proactive in identifying and addressing challenges.

You will join a dynamic, cross-functional team dedicated to advancing verification acceleration solutions for Synopsys’ strategic customers. The team comprises experts in HAV, simulation acceleration, R&D, product management, and applications engineering, all working collaboratively to define and deploy innovative methodologies.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Today, we stand at the beginning of the next era, the AI computing era, ignited by a new computing model, GPU deep learning. This new model - where deep neural networks are trained to recognize patterns from meaningful amounts of data - has shown to be deeply effective at solving the most sophisticated problems in everyday life.

As a Senior ASIC Verification Engineer at NVIDIA, you will verify the design and implementation of our innovative high speed coherent interconnects for our mobile SoCs and GPUs. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

Responsibilities:

• In this position, you will be responsible for verification of high-speed coherent interconnect design, architecture and golden models.
• You will be responsible for micro-architecture using sophisticated verification methodologies.
• As a member of our verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), complete test/coverage plans, and verify the correctness of the design. This role will collaborate with architects, designers, emulation, and silicon verification teams to accomplish your tasks.

Requirements:

• Bachelors or Master’s Degree (or equivalent experience)
• 3+ years of relevant verification experience
• Experience in architecting test bench environments for unit level verification
• Background in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Prior Design or Verification experience of Coherent high-speed interconnects
• Knowledge of industry standard interconnect protocols like PCIE, CXL, CHI will be useful
• Strong background developing TB's from scratch using SV and UVM methodology is desired
• C++ programming language experience, scripting ability and an expertise in System Verilog
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Strong debugging and analytical skills
• Experienced communication and interpersonal skills are required. A history of mentoring junior engineers and interns a huge plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers! We have some of the most forward-thinking and dedicated people in the world working for us. If you're creative and autonomous, we want to hear from you.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until March 13, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

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About the Team

We build foundational AI infrastructure that enables large-scale training and inference across diverse workloads and rapidly evolving hardware generations. Our work directly shapes how AI systems are designed, deployed, and scaled today and into the future. Engineers on this team operate with end-to-end ownership, deep technical rigor, and a strong bias toward real-world impact.

Microsoft Superintelligence Team

Microsoft Superintelligence team’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

This role is part of Microsoft AI’s Superintelligence Team. The MAIST is a startup-like team inside Microsoft AI, created to push the boundaries of AI toward Humanist Superintelligence—ultra-capable systems that remain controllable, safety-aligned, and anchored to human values. Our mission is to create AI that amplifies human potential while ensuring humanity remains firmly in control. We aim to deliver breakthroughs that benefit society—advancing science, education, and global well-being. We’re also fortunate to partner with incredible product teams giving our models the chance to reach billions of users and create immense positive impact. If you’re a brilliant, highly-ambitious and low ego individual, you’ll fit right in—come and join us as we work on our next generation of models!

Responsibilities

Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks. Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements. Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems. Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps. Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations. Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs. Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams. Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

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We pursue this mission through deep hardware–software co-design, combining rigorous systems thinking with hands-on engineering. The team invests heavily in understanding real production workloads large-scale training, inference, and emerging multimodal models and translating those insights into concrete improvements across the stack: from kernels, runtimes, and distributed systems, all the way down to silicon-level trade-offs and datacenter-scale architectures.

This role sits at the boundary between exploration and production. You will work closely with internal infrastructure, hardware, compiler, and product teams, as well as external partners across the hardware and systems ecosystem. Our operating model emphasizes rapid ideation and prototyping, followed by disciplined execution to drive high-leverage ideas into production systems that operate at massive scale.

In addition to delivering real-world impact on large-scale AI platforms, the team actively contributes to the broader research and engineering community. Our work aligns closely with leading communities in ML systems, distributed systems, computer architecture, and high-performance computing, and we regularly publish, prototype, and open-source impactful technologies where appropriate.

Microsoft Superintelligence Team Microsoft Superintelligence team’s mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

This role is part of Microsoft AI’s Superintelligence Team. The MAIST is a startup-like team inside Microsoft AI, created to push the boundaries of AI toward Humanist Superintelligence—ultra-capable systems that remain controllable, safety-aligned, and anchored to human values. Our mission is to create AI that amplifies human potential while ensuring humanity remains firmly in control. We aim to deliver breakthroughs that benefit society—advancing science, education, and global well-being. We’re also fortunate to partner with incredible product teams giving our models the chance to reach billions of users and create immense positive impact.

Responsibilities Lead the co-design of AI systems across hardware and software boundaries, spanning accelerators, interconnects, memory systems, storage, runtimes, and distributed training/inference frameworks.

Drive architectural decisions by analyzing real workloads, identifying bottlenecks across compute, communication, and data movement, and translating findings into actionable system and hardware requirements.

Co-design and optimize parallelism strategies, execution models, and distributed algorithms to improve scalability, utilization, reliability, and cost efficiency of large-scale AI systems.

Develop and evaluate what-if performance models to project system behavior under future workloads, model architectures, and hardware generations, providing early guidance to hardware and platform roadmaps.

Partner with compiler, kernel, and runtime teams to unlock the full performance of current and next-generation accelerators, including custom kernels, scheduling strategies, and memory optimizations.

Influence and guide AI hardware design at system and silicon levels, including accelerator microarchitecture, interconnect topology, memory hierarchy, and system integration trade-offs.

Lead cross-functional efforts to prototype, validate, and productionize high-impact co-design ideas, working across infrastructure, hardware, and product teams.

Mentor senior engineers and researchers, set technical direction, and raise the overall bar for systems rigor, performance engineering, and co-design thinking across the organization.

Qualifications Bachelor’s Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Additional or Preferred Qualifications Master’s Degree in Computer Science or related technical field AND 8+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR Bachelor’s Degree in Computer Science or related technical field AND 12+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Strong background in one or more of the following areas: AI accelerator or GPU architectures Distributed systems and large-scale AI training/inference High-performance computing (HPC) and collective communications ML systems, runtimes, or compilers Performance modeling, benchmarking, and systems analysis Hardware–software co-design for AI workloads Proficiency in systems-level programming (e.g., C/C++, CUDA, Python) and performance-critical software development.

Proven ability to work across organizational boundaries and influence technical decisions involving multiple stakeholders. Experience designing or operating large-scale AI clusters for training or inference. Deep familiarity with LLMs, multimodal models, or recommendation systems, and their systems-level implications. Experience with accelerator interconnects and communication stacks (e.g., NCCL, MPI, RDMA, high-speed Ethernet or InfiniBand). Background in performance modeling and capacity planning for future hardware generations. Prior experience contributing to or leading hardware roadmaps, silicon bring-up, or platform architecture reviews. Publications, patents, or open-source contributions in systems, architecture, or ML systems are a plus.

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Design Verification Engineer

Location

San Francisco

Employment Type

Full time

Location Type

Hybrid

Department

Scaling

Compensation

• $226K – $445K • Offers Equity

The base pay offered may vary depending on multiple individualized factors, including market location, job-related knowledge, skills, and experience. If the role is non-exempt, overtime pay will be provided consistent with applicable laws. In addition to the salary range listed above, total compensation also includes generous equity, performance-related bonus(es) for eligible employees, and the following benefits.

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

More details about our benefits are available to candidates during the hiring process.

This role is at-will and OpenAI reserves the right to modify base pay and other compensation components at any time based on individual performance, team or company results, or market conditions.

About the Team:

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale.

In this role you will:

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.

• Define verification plans based on architecture and microarchitecture specs.

• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.

• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.

• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

• Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

You might thrive in this role if you have:

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.

• Proven success verifying complex IP or SoC designs in industry-standard flows

• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).

• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

• Familiarity with performance modeling, formal verification, or emulation is a plus.

• Experience working in fast-paced, cross-disciplinary teams with a passion for building reliable hardware.

_To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations._

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

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About the Team

OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the Role

OpenAI's Hardware organization builds supercompute platforms from silicon and boards to full rack-scale systems to power advanced AI workloads. This role owns end-to-end quality for high-speed interconnect hardware across the product lifecycle: early design influence, supplier/contract manufacturer readiness, qualification, ramp, and fleet quality in lab and data center environments.

You will be the quality lead for advanced interconnect components and assemblies, including high-speed copper cables, cable cartridges, patch panels, backplane/cable-backplane solutions, high-speed connectors, and related electro-mechanical interfaces. You will partner closely with electrical, mechanical, SI/PI, systems, reliability, operations, and external vendors to prevent escapes and drive rapid, data-driven containment and corrective action.

Responsibilities

• Own quality for advanced interconnect components and assemblies: high-speed connectors, high-speed copper cables, cable cartridges (e.g., ultra-pass / cable cassette style assemblies), patch panels & optics, and backplane/cable-backplane interconnect solutions.

• Drive quality-by-design: participate in design reviews, DFM/DFx, tolerance stacks, material and plating selections, connector mating strategy, strain relief, and assembly methods to reduce variation and field failures.

• Define and track quality and reliability metrics (DPPM, yield, escapes, RMA/FRACAS trends, Cpk/Ppk where applicable) for interconnects across NPI and mass production.

• Build and execute qualification strategies for cables/connectors/patch panels (mechanical, environmental, electrical, and reliability), including test coverage, sample plans, clear pass/fail criteria, defining installation criteria and processes, optics termination quality management and setting fiber standards criteria.

• Partner with engineering and operations to drive smooth ramp: risk assessments, pilot build learnings, change control, and readiness reviews (EVT/DVT/PVT/MP or equivalent phases).

• Own supplier and CM performance management: scorecards, audits (process and quality system), and follow-up to close findings with verified effectiveness

• Work with suppliers to improve manufacturing throughput, stability, and yields for cable and connector assembly processes (e.g., wire prep, welding/crimping, overmolding/injection molding, plating, and assembly fixturing).

• Lead rapid containment and root-cause investigations for failures found during bring-up, system integration tests, reliability testing, and fleet deployments.

• Own the end-to-end corrective action process (8D, 5-Whys, Ishikawa, DOE as needed): define problem statements, isolate variables, validate root cause, implement fixes, and verify effectiveness.

• Partner with SI/PI and test teams to correlate electrical performance issues (e.g., link margin, BER, eye closure, impedance discontinuities, PAM4, TDR and VNA) with manufacturing and mechanical drivers (connector wear, plating, contamination, misalignment, cable routing, assembly variation).

• Support integration and deployment of OpenAI supercompute racks in lab and data center environments; identify quality risks tied to shipping, handling, installation, and service operations.

Requirements

• Bachelor's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.

• 5+ years of experience in quality engineering, with a focus on high-speed interconnects and electro-mechanical assemblies.

• Strong understanding of quality principles, including Six Sigma, Lean, and Design for Manufacturability (DFM).

• Experience with quality management systems, such as ISO 9001, and regulatory requirements, such as IEC 62368.

• Strong analytical and problem-solving skills, with the ability to analyze complex data and identify root causes.

• Excellent communication and collaboration skills, with the ability to work effectively with cross-functional teams.

• Experience with test and measurement equipment, such as oscilloscopes, signal generators, and network analyzers.

• Familiarity with simulation tools, such as ANSYS and COMSOL.

• Experience with data analysis and visualization tools, such as Excel, Python, and Tableau.

Preferred Qualifications

• Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, or related field.

• 8+ years of experience in quality engineering, with a focus on high-speed interconnects and electro-mechanical assemblies.

• Experience with advanced quality tools, such as Failure Mode and Effects Analysis (FMEA) and Design of Experiments (DOE).

• Familiarity with artificial intelligence and machine learning concepts and applications.

• Experience with cloud-based quality management systems, such as Salesforce and ServiceNow.

Salary and Benefits

• Salary: $123K – $285K

• Offers Equity

• Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts

• Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)

• 401(k) retirement plan with employer match

• Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)

• Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees

• 13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)

• Mental health and wellness support

• Employer-paid basic life and disability coverage

• Annual learning and development stipend to fuel your professional growth

• Daily meals in our offices, and meal delivery credits as eligible

• Relocation support for eligible employees

• Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.

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Microsoft AI are looking for a talented Member of Technical Staff, Hardware Health, to ensure these systems deliver sustained reliability, performance, and availability across exascale-class deployments.

About the Role

We work closely with research, hardware, datacenter, and platform engineering teams to develop predictive health models, failure detection frameworks, and autonomous remediation systems that keep our AI clusters operating at frontier scale. Our team is responsible for Copilot, Bing, Edge, and generative AI research.

Accountabilities

• Design and develop next-generation hardware health monitoring and diagnostic frameworks for large GPU clusters (NVL16/NVL72/GB200+ scale).
• Build predictive analytics pipelines leveraging telemetry, power, and thermal data to anticipate hardware degradation and systemic issues.
• Collaborate with silicon, firmware, and datacenter engineers to identify root causes and remediate large-scale hardware anomalies.
• Define system health KPIs (e.g., NIS/RIS, MTBF, failure domain analysis) and integrate them into real-time observability platforms.
• Lead incident triage for high-impact GPU, network, and cooling issues across distributed clusters.
• Drive automation in health management to reduce manual intervention to the top 5% of anomalies.
• Partner with cross-functional teams to influence hardware design for reliability, thermal efficiency, and serviceability.

The Candidate we're looking for

Experience:

• Bachelor's Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Technical skills:

• Experience working with large-scale HPC or GPU systems (NVIDIA H100/GB200 or equivalent).
• Deep understanding of GPU architecture, high-speed interconnects (NVLink, InfiniBand, RoCE), and large datacenter topologies.
• Proficiency in hardware telemetry, diagnostics, or failure analysis tools.

Personal attributes:

• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Benefits

• Competitive salary.
• Comprehensive benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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Microsoft AI are looking for a talented Member of Technical Staff, Hardware Health, to ensure these systems deliver sustained reliability, performance, and availability across exascale-class deployments.

About the Role

We work closely with research, hardware, datacenter, and platform engineering teams to develop predictive health models, failure detection frameworks, and autonomous remediation systems that keep our AI clusters operating at frontier scale. Our team is responsible for Copilot, Bing, Edge, and generative AI research.

Accountabilities

• Design and develop next-generation hardware health monitoring and diagnostic frameworks for large GPU clusters (NVL16/NVL72/GB200+ scale).
• Build predictive analytics pipelines leveraging telemetry, power, and thermal data to anticipate hardware degradation and systemic issues.
• Collaborate with silicon, firmware, and datacenter engineers to identify root causes and remediate large-scale hardware anomalies.
• Define system health KPIs (e.g., NIS/RIS, MTBF, failure domain analysis) and integrate them into real-time observability platforms.
• Lead incident triage for high-impact GPU, network, and cooling issues across distributed clusters.
• Drive automation in health management to reduce manual intervention to the top 5% of anomalies.
• Partner with cross-functional teams to influence hardware design for reliability, thermal efficiency, and serviceability.

The Candidate we're looking for

Experience:

• Bachelor's Degree in Computer Science or related technical field AND 6+ years technical engineering experience with coding in languages including, but not limited to, C, C++, C#, Java, JavaScript, or Python OR equivalent experience.

Technical skills:

• Experience working with large-scale HPC or GPU systems (NVIDIA H100/GB200 or equivalent).
• Deep understanding of GPU architecture, high-speed interconnects (NVLink, InfiniBand, RoCE), and large datacenter topologies.
• Proficiency in hardware telemetry, diagnostics, or failure analysis tools.

Personal attributes:

• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Benefits

• Competitive salary.
• Comprehensive benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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What you'll do

• Leading end-to-end deployment and integration of Verification IP at strategic customer accounts, ensuring seamless adoption and success.
• Defining and implementing robust verification strategies for Arm-based SoCs, with a focus on interconnect and coherency protocol validation.

What you need

• Deep expertise in UVM, SystemVerilog, and advanced protocol verification methodologies.
• Hands-on experience with Verification IPs (VIPs) and Transactors in both simulation and emulation environments.

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