You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.

Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.

Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.

Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.

Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

Conducting design reviews and offering constructive feedback to enhance quality and performance.

Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.

Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.

Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.

Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.

Fostering collaboration across global teams, leading to improved methodologies and best practices.

Maintaining the highest standards of quality, compliance, and performance in every design delivered.

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Architect, AI Solutions – Digital IP Methodology & Solutions

Sunnyvale, California, United States

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Hire Type EmployeeJob ID 17037Base Salary Range $208000-$312000Date posted 04/21/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 20+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.

You excel in dynamic, high-performance teams, proactively sharing knowledge and mentoring peers. Your communication skills enable you to translate technical complexities into actionable insights for both customers and colleagues. You are innovative, adaptable, and eager to stay ahead in a fast-evolving domain. Your passion for continuous learning and improvement drives you to explore new methodologies, ensuring customer success and the advancement of Synopsys’ cutting-edge tools.

Above all, you are motivated by the impact of your work on the semiconductor industry and the broader technology landscape. You are ready to be a technical leader and trusted advisor, shaping the future of physical design and pushing the boundaries of what’s possible.

What You’ll Be Doing:

• Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

• Collaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.

• Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.

• Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.

• Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.

The Impact You Will Have:

• Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.

• Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.

• Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.

• Position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.

• Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.

• Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.

What You’ll Need:

• Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.

• 15+ plus years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.

• Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.

• In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.

• Experience with LLMs, GPT models, and other generative AI techniques.

• Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.

Who You Are:

• Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.

• Excellent communicator, able to clearly articulate technical concepts to diverse audiences.

• Collaborative team player who thrives in a fast-paced, cross-functional environment.

• Customer-focused mindset with a passion for delivering exceptional support and building lasting relationships.

• Effective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.

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As a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.

Key responsibilities include:

• Designing and developing standard cell layouts
• Applying comprehensive sign-off checks
• Collaborating with global teams to resolve methodology issues and implement optimized layout designs
• Conducting design reviews and offering constructive feedback to enhance quality and performance

You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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Your responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

You will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

The impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.

To succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.

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What you'll do

• The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.
• In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

What you need

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys' industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

What you need

Bachelor's and/or Master's degree in Electrical Engineering or a related field.

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