Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.
\nJob Description
\nAs an experienced Analog Layout Senior Engineer, you will work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees. You will floor plan, power design, signal routing strategy, EMIR awareness, and parasitic optimization for layout blocks from schematics. You will apply Analog Layout techniques to ensure design meets performance with minimum area and good yield. You will build and enhance layout flow for faster, higher quality design processes.
\nResponsibilities
\nImpact
\nRequirements
\nTeam
\nYou will join a dynamic and innovative team focused on developing high-performance Analog IPs. Our team collaborates closely with colleagues in Vietnam, USA, Canada, and other countries to ensure the success of our products. We value teamwork, knowledge sharing, and continuous improvement, and we are committed to fostering a supportive and inclusive work environment.
\nRewards and Benefits
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nCollaborating with local and international teams to develop layouts for complex analog and mixed-signal designs in advanced technology nodes (3nm, 2nm, and beyond).
\nUtilizing Synopsys suite of tools and full custom analog layout design tools (e.g., Custom Compiler) to create and optimize circuit layouts.
\nImplementing and verifying designs using industry-leading verification tools such as ICV, Calibre and Star-RCXT...
\nDeveloping SERDES sub-circuit layouts (RX, TX, PLL, etc.) and optimizing for signal integrity, including clock/data routes, differential routing, and shielding.
\nApplying scripting techniques (TCL, Python, etc.) to automate layout processes and improve workflow efficiency.
\nEnsuring designs meet ESD constraints, mitigate latch-up risks, and optimize for reliability issues such as EM and IR drop.
\nDesigning custom digital logic cell layouts and associated logic path routing for mixed-signal integration.
\nRefining layouts to minimize parasitic effects and enhance matching, reliability, and performance.
\nDelivering high-quality IP that powers next-generation semiconductor products for global customers.
\nEnabling Synopsys to maintain leadership in advanced technology node design and IP development.
\nContributing to the creation of reliable, high-performance silicon chips used in communications.
\nDriving innovation in analog and mixed-signal layout methodologies and tools.
\nEnhancing cross-team collaboration and knowledge sharing to accelerate project timelines and improve outcomes.
\nEnsuring robust design practices that minimize risk and maximize reliability, meeting stringent industry standards.
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\nDefining and deploying advanced layout methodologies that accelerate execution, enhance quality, and promote standardized best practices across global teams.
\nGathering customer requirements, translating them into clear technical specifications, and ensuring these specifications drive methodology and workflow development.
\nDeveloping end-to-end workflows that enhance quality, consistency, and efficiency across Synopsys IP development.
\nCollaborating closely with cross-functional teams—including Circuit Design, Physical Design, CAD, Product Engineering, and Quality—to enable adoption of methodologies for advanced technology nodes.
\nProviding technical leadership across distributed teams, aligning planning and execution to meet project goals.
\nDefining, tracking, and analyzing performance metrics to drive continuous improvement and influence future methodology strategy.
\nCreating and maintaining comprehensive documentation to ensure clarity, scalability, and long-term usability.
\nEngaging with internal partners and external customers as a trusted technical representative of the Methodology Team.
\nLeading innovation in analog/mixed-signal layout flows, combining industry-standard tools and internal automation to validate and evolve methodologies.
\nMentoring and supporting junior engineers, enabling skill growth and knowledge sharing across the organization.
\nAccelerating and improving the reliability of analog/mixed-signal IP development at advanced nodes.
\nDriving alignment and quality across global design teams through standardized workflows and strong technical leadership.
\nStrengthening collaboration and knowledge transfer across engineering disciplines.
\nInfluencing organizational and product strategy through methodology innovation and customer insights.
\nIncreasing transparency and maintainability of workflows through high-quality documentation.
\nContributing to reinforcing Synopsys’ position as a leader in semiconductor design technology.
\n5+ years in analog/mixed-signal layout or ASIC physical design, with experience in FinFET and advanced nodes strongly preferred.
\nDeep knowledge of analog and mixed-signal CMOS layout, device-level considerations, and chip-level integration.
\nStrong expertise with industry tools such as Synopsys Custom Compiler, Cadence Virtuoso, ICV, Calibre, and related verification flows.
\nProven ability to gather customer requirements and convert them into technical specifications.
\nDemonstrated experience building workflows that improve IP quality, efficiency, and consistency.
\nStrong organizational skills, attention to detail, and ability to manage multiple complex initiatives simultaneously.
\nExcellent communication, leadership, and mentoring abilities.
\nInnovative and proactive in solving complex engineering challenges.
\nCollaborative, with a talent for working across interdisciplinary teams.
\nStrategic thinker who balances technical depth with big-picture vision.
\nEffective communicator, able to convey technical concepts to diverse audiences.
\nMentor and coach, dedicated to supporting the growth of others.
\nAdaptable and resilient in fast-paced and evolving environments.
\nYou will join the Mixed Signal IP Technology and Methodology Team—an advanced physical design group focused on developing full-custom analog and ASIC layout solutions for high-speed integrated circuits. The team is known for its collaborative culture, cutting-edge tool ecosystem, and strong commitment to innovation. As a Staff Engineer, you’ll work closely with experienced layout engineers, CAD specialists, and circuit designers to help define best-in-class methodologies and deliver high-quality solutions for Synopsys’ global customers.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
\nSynopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact hr-help-canada@synopsys.com.
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\nYou are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.
\nYour technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.
\nYou will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.
\nYou will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.
\nYou will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.
\nYou will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.
\nYou will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.
\nYou will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.
\nYou will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.
\nYou will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.
\nWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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\nWhat you'll do
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\nWhat you'll do
\nEngaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.
\nWhat you need
\nBachelor's and/or Master's degree in Electrical Engineering or a related field.
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