We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.

Key Responsibilities:

• Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes
• Driving timing closure efforts, especially above ~2GHz
• Resolving complex challenges related to mixed signal and macro IP integration
• Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements
• Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams
• Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects
• Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation

Requirements:

• Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications
• Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)
• Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration
• Strong analytical and problem-solving skills, with a track record of resolving complex technical issues
• Ability to independently lead project tasks, mentor junior team members, and work collaboratively

Benefits:

• Comprehensive medical and healthcare plans
• Time away from work for vacation, sick leave, and family care
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP (Employee Stock Purchase Plan)
• Retirement plans
• Competitive salaries

XML job scraping automation by YubHub

You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.

Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.

Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.

Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.

Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

Conducting design reviews and offering constructive feedback to enhance quality and performance.

Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.

Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.

Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.

Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.

Fostering collaboration across global teams, leading to improved methodologies and best practices.

Maintaining the highest standards of quality, compliance, and performance in every design delivered.

XML job scraping automation by YubHub

At Synopsys, we drive the innovations that shape the way the world lives, works, and connects. Our technology is foundational to the Era of Pervasive Intelligence,from autonomous systems and high-performance computing to artificial intelligence and advanced connectivity.

As a global leader in electronic design automation, semiconductor IP, and system design solutions, we enable customers to deliver complex, high-performance silicon and software products with confidence.

Technical & Program Leadership

• Lead and oversee end-to-end SoC physical design execution, from specification through post-silicon bring-up, using Synopsys EDA tools and IP.
• Provide technical direction and architectural guidance on Place & Route, timing closure, power integrity (IREM), extraction, and physical verification.
• Act as a senior escalation point for complex technical challenges, driving resolution through sound engineering judgment.
• Ensure consistent delivery excellence across turnkey projects and customer advisory engagements.
• Influence and evolve design methodologies and best practices within the broader SoC organization.

People Management & Team Development

• Build, lead, and develop a high-performing SoC design team in Vietnam, including hiring, onboarding, coaching, and performance management.
• Establish clear goals, expectations, and development plans aligned with Synopsys’ engineering and leadership frameworks.
• Mentor senior engineers and cultivate future technical and people leaders to support long-term capability growth.
• Foster a culture of technical rigor, accountability, inclusion, and continuous improvement.

Stakeholder & Business Partnership

• Partner closely with Business Units, R&D, and Sales to align engineering execution with product strategy and customer needs.
• Serve as a trusted technical advisor to customers, customer design teams, and internal stakeholders.
• Contribute to workforce planning, delivery commitments, and risk management within the Vietnam organization.
• Play a key role in scaling and strengthening Synopsys’ SoC engineering capability in Vietnam as part of the global organization.

The Impact You Will Have

• Enable scalable, high-quality delivery of advanced SoC designs.
• Elevate technical capability and execution maturity within Synopsys Vietnam.
• Drive innovation in physical design methodology and engineering best practices.
• Improve customer satisfaction through strong technical leadership and trusted advisory support.
• Develop and retain critical engineering talent in a highly competitive semiconductor market.
• Strengthen Synopsys’ reputation as a long-term technology and talent leader in Vietnam.

XML job scraping automation by YubHub

Key Responsibilities:

• Design and implement physical design flows for SLM IPs and subsystems, including state-of-the-art SLM Controllers and on-chip Monitors.
• Execute RTL2GDS flows on advanced process nodes (16nm to 3nm and beyond), ensuring robust performance and reliability.
• Perform static timing analysis, synthesis, and layout closure using industry-leading EDA tools, preferably Synopsys PrimeTime, ICC2, Design Compiler, or Fusion Compiler.
• Collaborate with cross-functional teams to integrate soft and mixed-signal IPs, optimize design margins, and address high-frequency, multi-voltage, and low-power requirements.
• Develop and enhance automation scripts (TCL/PERL) to streamline design processes and improve execution efficiency.
• Participate in project planning, execution, and mentoring, supporting both internal teams and external customers with technical expertise and guidance.
• Contribute to the signoff and verification of designs, ensuring compliance with quality and reliability standards.

Impact:

• Accelerate the integration and deployment of next-generation SLM products, enabling customers to bring differentiated solutions to market faster and with reduced risk.
• Optimize semiconductor lifecycle management through innovative hardware IP, test, and analytics, enhancing performance, power, area, and yield.
• Drive advancements in chip design and verification methodologies, supporting the evolution of process nodes and IP integration.
• Enhance reliability and scalability of technology products, contributing to breakthroughs in AI, IoT, automotive, and cloud sectors.
• Empower global teams and customers with robust solutions, technical guidance, and effective collaboration.
• Support Synopsys' leadership in the Era of Smart Everything, powering the technologies that shape our connected world.

Requirements:

• Strong experience in standard ASIC RTL2GDS physical implementation and signoff flows.
• Hands-on expertise in synthesis, pre-layout STA, post-layout STA, and CTS tools.
• BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience.
• Automation-focused mindset with proven experience in scripting (TCL/PERL) and custom flow development.
• Exposure to soft and mixed-signal IPs, high-frequency/multi-voltage designs, and low-power methodologies.
• Proficiency with EDA tools from any vendor, preferably Synopsys tools (PrimeTime, ICC2, Design Compiler, Fusion Compiler).
• Solid understanding of OCV, POCV, derates, crosstalk, and design margins.
• Experience in layout of digital blocks, timing constraints, STA, and timing closure.
• Experience with PVT-sensors and/or DFT/DFx technologies is a strong plus.

Who You Are:

• Collaborative and inclusive team player who values diversity and supports others.
• Excellent communicator, able to convey complex technical concepts clearly and effectively.
• Mentor and leader, providing guidance and support to peers and junior engineers.
• Adaptable and innovative, eager to learn and embrace new technologies and methodologies.
• Self-motivated with strong project execution and planning skills.
• Customer-focused, dedicated to delivering high-quality solutions and support.

The Team You’ll Be A Part Of:

You’ll join the rapidly expanding Hardware-Analytics and Test (HAT) business unit as a member of the SLM Hardware Group (SHG). The team is dedicated to developing advanced SLM IPs and subsystems, leveraging expertise in backend and physical design to deliver robust, high-performance solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

As a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.

Key responsibilities include:

• Designing and developing standard cell layouts
• Applying comprehensive sign-off checks
• Collaborating with global teams to resolve methodology issues and implement optimized layout designs
• Conducting design reviews and offering constructive feedback to enhance quality and performance

You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

XML job scraping automation by YubHub

Your responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

You will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

The impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.

To succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.

XML job scraping automation by YubHub

Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.

You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

As a member of our high-performing Customer Application Services team, you will collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.

Responsibilities:

• Support customers in enjoying Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge.
• Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).
• Collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.
• Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.
• Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.

Key Qualifications:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),
• Tool knowledge (preferred): STA (Primetime, Tempus)

XML job scraping automation by YubHub

They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

As a Senior ASIC Physical Design Engineer, you will be responsible for implementing and integrating state-of-the-art DDR IPs at advanced technology nodes (10nm, 7nm, 6nm, and below).

You will drive timing closure for high-frequency designs (above ~4GHz), ensuring optimal performance and reliability.

You will collaborate with local and US-based teams, engaging in daily technical discussions to align on project goals and challenges.

You will integrate mixed-signal hard macro IPs and address unique integration requirements with innovative solutions.

You will design and build efficient clock trees, focusing on tight skew balancing and robust clock distribution.

You will participate in design reviews, debug issues, and contribute to continuous improvement of physical design methodologies.

You will support the implementation of best practices in floorplanning, placement, routing, and power optimization.

You will mentor junior engineers and contribute to team knowledge sharing initiatives.

Impact

You will enable delivery of high-performance DDR IPs that power next-generation consumer and enterprise products.

You will advance Synopsys' leadership in IP implementation at cutting-edge technology nodes.

You will champion best-in-class timing closure and integration practices, raising the bar for design excellence.

You will facilitate seamless cross-site collaboration, ensuring global project success.

You will drive innovation in clock tree synthesis and mixed-signal integration, contributing to differentiated product offerings.

You will accelerate time-to-market for customers by delivering robust, silicon-proven IP solutions.

Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, or related field.

3+ years of experience in ASIC physical design, especially at advanced technology nodes (10nm, 7nm, 6nm or below).

Proficiency with physical design tools (such as Synopsys ICC2, PrimeTime, StarRC, etc.).

Solid understanding of timing closure, clock tree synthesis, and skew balancing for high-frequency designs.

Experience with DDR interface implementation and/or mixed-signal IP integration is highly desirable.

Familiarity with scripting languages (Tcl, Perl, Python) for automation and workflow optimization.

Strong analytical and debugging skills for addressing complex design challenges.

Team

You will join the Synopsys DDR IP implementation team, a group of passionate engineers focused on delivering world-class memory interface solutions at the leading edge of semiconductor technology.

The team fosters a culture of innovation, technical excellence, and collaboration, working closely with global counterparts to achieve ambitious project goals.

Together, you will help shape the future of high-performance silicon and enable the next wave of intelligent systems.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

XML job scraping automation by YubHub

Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

16005

Remote Eligible

No

Date Posted

03/05/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.

What You’ll Be Doing:

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.

• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

• Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.

• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

• Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.

• Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.

The Impact You Will Have:

• Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.

• Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development.

• Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.

• Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.

• Elevate the technical capabilities of the application engineering team through mentorship and cross-training.

• Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.

• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).

• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.

• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.

• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.

• Outstanding verbal and written communication, presentation, and customer interaction skills.

Who You Are:

• Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.

• Analytical thinker with a problem-solving mindset and a passion for continuous improvement.

• Adaptable and resilient in the face of evolving customer requirements and technology landscapes.

• Strong organizational skills, able to manage multiple projects and priorities with poise.

• Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.

The Team You’ll Be A Part Of:

You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

XML job scraping automation by YubHub

What you'll do

• Design and implement SoC solutions using Synopsys EDA tools and IP.
• Advise customer design and CAD teams.

What you need

• BS/MS/PhD in relevant engineering fields.
• 7+ years in Place & Route with Fusion Compiler/ICC2.

XML job scraping automation by YubHub

What you'll do

• The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.
• In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

What you need

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

XML job scraping automation by YubHub

What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

XML job scraping automation by YubHub

What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 4 to 7+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

XML job scraping automation by YubHub