Job Description

We are seeking a highly skilled Layout Design Senior Engineer to join our team. As a Layout Design Senior Engineer, you will be responsible for developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below).

Responsibilities

• Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below)
• Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements.
• Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles.
• Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues.
• Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area
• Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes.
• Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.

Impact

• Accelerating the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products.
• Ensuring robust and reliable IP performance through meticulous layout design and physical verification.
• Driving innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more.
• Contributing to the world’s broadest portfolio of silicon IP, enhancing Synopsys’ position as a technology leader.
• Reducing risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements.
• Fostering a culture of collaboration, accountability, and technical excellence within the team and across the organization.
• Helping shape the next wave of semiconductor advancements, powering smart devices and connected systems globally.

Requirements

• BTech/MTech degree in Electronics, Electrical, or related engineering discipline.
• 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below).
• Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies.
• Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies.
• Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation.
• Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms.
• Ability to work independently and collaboratively, managing multiple tasks and priorities.

Team

You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world’s most advanced chips and devices.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a passionate and detail-oriented engineer with deep expertise in IC layout design, eager to contribute to the development of next-generation DDR & HBM PHY IPs. Your experience in advanced process technologies equips you with a strong foundation in deep submicron effects, layout floorplanning, and physical verification. You thrive in dynamic environments, bringing a collaborative spirit and a growth mindset to every project. You value diversity and inclusion, recognizing the importance of varied perspectives in driving innovation. With a commitment to accountability, you consistently deliver quality results, demonstrating ownership and initiative in your work. Your communication skills,both verbal and written,enable you to effectively share ideas, provide feedback, and partner with cross-functional teams. You are motivated by the opportunity to work on cutting-edge technologies, always seeking to expand your knowledge and make a meaningful impact. Whether solving complex problems or optimizing layouts for performance, power, and area, you approach challenges with creativity and perseverance. You are ready to join Synopsys in shaping the future of silicon IP, contributing to products that empower customers to succeed in the Era of Smart Everything.

Developing high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below) Desining layout floorplans, routing, and conducting physical verifications to ensure compliance with industry standards and internal quality requirements. Performing DRC, LVS, ERC, Antenna checks, and ensuring timely completion of verification cycles. Applying layout matching techniques and addressing ESD, latch-up, EMIR, DFM, and LEF generation issues. Collaborating closely with cross-disciplinary teams to optimize layout for performance, power, and area Troubleshooting and debugging layout challenges, continually improving methodologies and design outcomes. Documenting design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement.

XML job scraping automation by YubHub

As a Layout Design Senior Engineer, you will develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below). You will design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements.

Responsibilities:

• Develop high-quality layouts for DDR and HBM PHY IPs using advanced CMOS, FinFET, and GAA process technologies (7nm and below)
• Design layout floorplans, routing, and conduct physical verifications to ensure compliance with industry standards and internal quality requirements
• Perform DRC, LVS, ERC, Antenna checks, and ensure timely completion of verification cycles
• Apply layout matching techniques and address ESD, latch-up, EMIR, DFM, and LEF generation issues
• Collaborate closely with cross-disciplinary teams to optimize layout for performance, power, and area
• Troubleshoot and debug layout challenges, continually improving methodologies and design outcomes
• Document design flows, methodologies, and best practices to facilitate knowledge sharing and continuous improvement

Impact:

• Accelerate the integration of advanced silicon IP into customer SoCs, enabling rapid time-to-market with differentiated products
• Ensure robust and reliable IP performance through meticulous layout design and physical verification
• Drive innovation in memory interface IPs, supporting the demands of AI, cloud computing, IoT, and more
• Contribute to the world's broadest portfolio of silicon IP, enhancing Synopsys' position as a technology leader
• Reduce risk for customers by delivering high-quality, verified IP solutions that meet stringent requirements
• Foster a culture of collaboration, accountability, and technical excellence within the team and across the organization
• Help shape the next wave of semiconductor advancements, powering smart devices and connected systems globally

Requirements:

• B.Tech/M.Tech degree in Electronics, Electrical, or related engineering discipline
• 2+ years of hands-on experience in IC layout development for advanced process nodes (7nm and below)
• Expertise in DRC, LVS, ERC, Antenna checks, and physical verification methodologies
• Strong understanding of deep submicron effects, floorplan techniques, and layout matching in CMOS, FinFET, GAA technologies
• Experience with ESD, latch-up prevention, EMIR analysis, DFM considerations, and LEF generation
• Proficiency with layout tools such as Cadence Virtuoso, Synopsys Custom Compiler, or similar EDA platforms
• Ability to work independently and collaboratively, managing multiple tasks and priorities

Team:

You will join a dynamic and innovative team within the Silicon IP group, focused on developing industry-leading DDR & HBM PHY IPs. Our team thrives on collaboration, technical excellence, and a shared vision to push the boundaries of semiconductor technology. You will work alongside experts in layout, verification, and system integration, contributing to solutions that power the world's most advanced chips and devices.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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