{"version":"0.1","company":{"name":"YubHub","url":"https://yubhub.co","jobsUrl":"https://yubhub.co/jobs/skill/ic-compiler"},"x-facet":{"type":"skill","slug":"ic-compiler","display":"Ic Compiler","count":10},"x-feed-size-limit":100,"x-feed-sort":"enriched_at desc","x-feed-notice":"This feed contains at most 100 jobs (the most recently enriched). For the full corpus, use the paginated /stats/by-facet endpoint or /search.","x-generator":"yubhub-xml-generator","x-rights":"Free to redistribute with attribution: \"Data by YubHub (https://yubhub.co)\"","x-schema":"Each entry in `jobs` follows https://schema.org/JobPosting. YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_524edc8e-463"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Staff Engineer in ASIC Physical Design, you will contribute to the development of cutting-edge semiconductor solutions, working on complex tasks such as chip architecture, circuit design, and verification. You will be responsible for designing and implementing physical design flows, including floor planning, synthesis, placement and routing, timing closure, and physical verification.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>6 to 7 years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floorplanning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks -logic, memory, interfaces, analog, security, and embedded processors into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_524edc8e-463","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-staff-engineer-16723/44408/93743819104","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Floor planning","Synthesis","Placement and routing","Timing closure","IP integration","Test chip methodology","Advanced verification flows","CAD tools","Design Compiler","PrimeTime","IC Compiler II/FC","ICV","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:19:07.430Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Floor planning, Synthesis, Placement and routing, Timing closure, IP integration, Test chip methodology, Advanced verification flows, CAD tools, Design Compiler, PrimeTime, IC Compiler II/FC, ICV, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cd352346-abd"},"title":"ASIC Physical Design, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutionsΈ. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes</li>\n<li>Driving timing closure efforts, especially above ~2GHz</li>\n<li>Resolving complex challenges related to mixed signal and macro IP integration</li>\n<li>Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements</li>\n<li>Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams</li>\n<li>Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects</li>\n<li>Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications</li>\n<li>Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)</li>\n<li>Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration</li>\n<li>Strong analytical and problem-solving skills, with a track record of resolving complex technical issues</li>\n<li>Ability to independently lead project tasks, mentor junior team members, and work collaboratively</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans</li>\n<li>Time away from work for vacation, sick leave, and family care</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>ESPP (Employee Stock Purchase Plan)</li>\n<li>Retirement plans</li>\n<li>Competitive salaries</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cd352346-abd","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/asic-physical-design-staff-engineer/44408/94169001536","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","DDR/HBM/HBI IP integration","Timing closure","Mixed signal and macro IP integration","Clock tree design"],"x-skills-preferred":["Design Compiler (DC)","IC Compiler II (ICC2)","PrimeTime SI (PT-SI)","Formality (FC)"],"datePosted":"2026-04-24T14:16:07.686Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, DDR/HBM/HBI IP integration, Timing closure, Mixed signal and macro IP integration, Clock tree design, Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), Formality (FC)"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_e7b7b30e-53e"},"title":"Staff Applications Engineer (Backend)","description":"<p>As a Staff Applications Engineer in Ho Chi Minh City, you&#39;ll partner with customers and internal teams to deploy and optimize Synopsys backend implementation solutions, drive PPA outcomes, and accelerate successful adoption of methodologies across advanced technology nodes.</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Driving customer success on RTL-to-GDSII implementation flows with focus on PPA (performance, power, area)</li>\n<li>Owning/leading technical execution on key topics: physical synthesis, timing closure, CTS, routing</li>\n<li>Troubleshooting complex design/tool issues, reproducing, isolating, and driving resolution with R&amp;D</li>\n<li>Building/standardizing methodologies; automating workflows using Tcl and Python (or Perl/Tcl where applicable)</li>\n<li>Delivering technical trainings, best practices, application notes, and customer-facing presentations</li>\n<li>Collaborating cross-functionally with R&amp;D, Product, and worldwide AE teams to influence features and improve product quality</li>\n</ul>\n<p>Requirements include:</p>\n<ul>\n<li>BS/MS in Electrical Engineering, Computer Engineering, or related field, with 5+ years relevant experience</li>\n<li>Strong hands-on knowledge of RTL-to-GDSII and backend implementation</li>\n<li>Experience with Fusion Compiler, IC Compiler II (ICC2) or similar P&amp;R tools</li>\n<li>Solid understanding of timing analysis/closure, CTS, routing, and advanced nodes</li>\n<li>Scripting skills in Tcl and Python for automation and productivity</li>\n<li>Strong communication skills in English; comfortable working with global customers/teams</li>\n</ul>\n<p>You&#39;ll be successful if you&#39;re analytical, structured, and calm under pressure when debugging complex issues, proactive in driving alignment across customers, AE peers, and R&amp;D, comfortable juggling multiple priorities while maintaining high execution quality, and curious and continuously learning new flows, nodes, and AI-enabled productivity approaches.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_e7b7b30e-53e","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/staff-applications-engineer-backend/44408/94297252352","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["RTL-to-GDSII","backend implementation","Fusion Compiler","IC Compiler II","physical synthesis","timing closure","CTS","routing","Tcl","Python"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:15:28.613Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"RTL-to-GDSII, backend implementation, Fusion Compiler, IC Compiler II, physical synthesis, timing closure, CTS, routing, Tcl, Python"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_cdd41515-ded"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p><strong>You Are:</strong></p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges.</p>\n<p>Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules.</p>\n<p><strong>What You’ll Be Doing:</strong></p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n</ul>\n<ul>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n</ul>\n<ul>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n</ul>\n<ul>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n</ul>\n<ul>\n<li>Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n</ul>\n<ul>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n</ul>\n<ul>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p><strong>The Impact You Will Have:</strong></p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n</ul>\n<ul>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n</ul>\n<ul>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n</ul>\n<ul>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n</ul>\n<ul>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n</ul>\n<ul>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_cdd41515-ded","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/94169001488","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimization","static timing analysis (STA)","physical verification","EMIR analysis","timing closure","block-level and full-chip floor-planning","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:15:21.802Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimization, static timing analysis (STA), physical verification, EMIR analysis, timing closure, block-level and full-chip floor-planning, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_c7ea2375-1cc"},"title":"ASIC Physical Design, Sr Director","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>As a Sr Director of ASIC Physical Design, you will own and drive the end-to-end physical design flow for high-speed die-to-die interconnect and interface chips targeting 2 GHz+ on advanced process nodes (sub-7nm/5nm/3nm).</p>\n<p>Key responsibilities include:</p>\n<ul>\n<li>Leading floorplanning, power planning, clock tree synthesis, place-and-route, and physical verification with emphasis on die-to-die interface placement and bump/pad ring constraints.</li>\n</ul>\n<ul>\n<li>Achieving timing closure across all corners and modes, with expertise in multi-corner multi-mode sign-off for high-speed serial and parallel interfaces.</li>\n</ul>\n<ul>\n<li>Driving power integrity, signal integrity, and thermal analysis to meet stringent tape-out criteria for high-bandwidth die-to-die links.</li>\n</ul>\n<ul>\n<li>Defining and owning physical design methodology, Synopsys tool flows, and best practices across the organization.</li>\n</ul>\n<ul>\n<li>Building, mentoring, and leading a globally distributed team, establishing effective communication and collaboration norms to foster cohesion and engineering excellence.</li>\n</ul>\n<ul>\n<li>Collaborating cross-functionally with RTL design, DV, architecture, CAD/EDA, and program management teams globally.</li>\n</ul>\n<ul>\n<li>Owning physical design schedules and milestones for multiple concurrent projects, communicating status to senior leadership and mitigating risks proactively.</li>\n</ul>\n<ul>\n<li>Championing automation and scripting to improve PPA outcomes and team productivity.</li>\n</ul>\n<p>The impact you will have:</p>\n<ul>\n<li>Enable the physical implementation of high-speed die-to-die interconnects that power large-scale AI accelerators, GPU clusters, and multi-die systems.</li>\n</ul>\n<ul>\n<li>Deliver ultra-low latency, high-bandwidth chip-to-chip communication at the core of next-generation AI infrastructure.</li>\n</ul>\n<ul>\n<li>Advance the adoption of cutting-edge process nodes and interface standards, positioning Synopsys as a leader in silicon innovation.</li>\n</ul>\n<ul>\n<li>Ensure robust engineering quality, execution velocity, and successful tape-outs across global teams.</li>\n</ul>\n<ul>\n<li>Drive organizational excellence by fostering a culture of accountability, growth, and technical mastery.</li>\n</ul>\n<ul>\n<li>Shape methodologies and tool flows that set industry benchmarks for high-speed, advanced-node physical design.</li>\n</ul>\n<ul>\n<li>Contribute to the strategic direction of AI silicon and interconnect products, impacting the broader technology ecosystem.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>15+ years of hands-on physical design experience, with deep expertise in high-frequency (≥2 GHz) chip design.</li>\n</ul>\n<ul>\n<li>Expertise with Synopsys IC Compiler II (ICC2), PrimeTime, Fusion Compiler, StarRC, IC Validator, and PrimePower.</li>\n</ul>\n<ul>\n<li>Track record of taping out high-speed interface ICs, die-to-die interconnect chips, SerDes, or similar designs at advanced process nodes (7nm, 5nm, 3nm).</li>\n</ul>\n<ul>\n<li>Understanding of die-to-die interface standards and protocols (UCIe, BoW, HBI, XSR, or proprietary) and their physical implementation.</li>\n</ul>\n<ul>\n<li>Experience with power intent flows (UPF/CPF), low-power design techniques, and dynamic/static power optimization.</li>\n</ul>\n<ul>\n<li>Strong scripting skills (Tcl, Python, Perl) for tool flow automation and PPA optimization.</li>\n</ul>\n<ul>\n<li>Proven ability to lead and grow globally distributed engineering teams of 10+ people.</li>\n</ul>\n<ul>\n<li>Cross-cultural communication and collaboration skills; experience working across US, Asia, or European engineering centers.</li>\n</ul>\n<ul>\n<li>BS or MS in Electrical Engineering, Computer Engineering, or related field (PhD preferred).</li>\n</ul>\n<p>As a Sr Director of ASIC Physical Design, you will join a globally distributed Silicon Engineering team focused on the physical implementation of cutting-edge AI silicon and high-speed die-to-die interconnects.</p>\n<p>Our team spans multiple sites and time zones, collaborating with process technology, packaging, RTL, DV, architecture, CAD/EDA, and program management teams.</p>\n<p>We pride ourselves on a culture of technical depth, low bureaucracy, and a relentless drive for engineering excellence.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p>Our total rewards include both monetary and non-monetary offerings.</p>\n<p>Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_c7ea2375-1cc","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/ho-chi-minh-city/asic-physical-design-sr-director-in-hcmc-da-nang/44408/93750516784","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC Physical Design","High-Frequency Chip Design","Synopsys IC Compiler II","PrimeTime","Fusion Compiler","StarRC","IC Validator","PrimePower","Die-to-Die Interface Standards","Power Intent Flows","Low-Power Design Techniques","Dynamic/Static Power Optimization","Scripting Skills (Tcl, Python, Perl)","Leadership and Team Management"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:13:37.968Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Ho Chi Minh City"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC Physical Design, High-Frequency Chip Design, Synopsys IC Compiler II, PrimeTime, Fusion Compiler, StarRC, IC Validator, PrimePower, Die-to-Die Interface Standards, Power Intent Flows, Low-Power Design Techniques, Dynamic/Static Power Optimization, Scripting Skills (Tcl, Python, Perl), Leadership and Team Management"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_642c88a4-a92"},"title":"ASIC Physical Design, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Sr Staff Engineer in ASIC Physical Design, you will contribute to the development of advanced semiconductor solutions, collaborating with cross-functional teams to design, verify, and manufacture complex SoCs and test chips. Your expertise in the physical design flow and familiarity with industry-leading tools will enable you to drive technical execution and lead complex projects.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Contributing to physical design implementation for test chips across DDR/HBM/UCIe protocols, from RTL to final GDS release to foundry.</li>\n<li>Developing overall floorplan and power/ground strategies tailored for diverse test chip architectures.</li>\n<li>Owning and optimizing the RTL-to-GDSII flow, ensuring design convergence for area, power, performance, and manufacturability.</li>\n<li>Executing and overseeing static timing analysis (STA) and physical verification (EM/IR drop, ERC/DRC/LVS, PERC/ESD analysis).</li>\n<li>Integrating updated covercells, circuit/IP/PLL/hard-macros, and coordinating abutment checking and QA/release of hard-macros.</li>\n<li>Driving tool flow automation and debugging to enhance productivity and design reliability.</li>\n<li>Collaborating closely with architecture, RTL, circuit, and covercell teams throughout test chip development.</li>\n</ul>\n<p>Impact:</p>\n<ul>\n<li>Enable robust validation of Synopsys&#39;s IP blocks for PHYs, ensuring high-quality deliverables prior to customer release or SoC integration.</li>\n<li>Accelerate time-to-market by driving rapid turnaround from RTL to silicon, reducing schedule risks and helping Synopsys meet critical market windows.</li>\n<li>Enhance product reliability and manufacturability through rigorous timing closure, power/thermal analysis, and comprehensive verification signoff.</li>\n<li>Bolster Synopsys&#39;s reputation by delivering high-quality, silicon-proven IP that meets real-world performance and reliability standards.</li>\n<li>Foster seamless cross-functional collaboration, bridging architects, RTL designers, verification teams, and silicon validation groups.</li>\n<li>Champion continuous process and tool improvement, implementing flow automation to keep Synopsys at the forefront of EDA innovation.</li>\n</ul>\n<p>Requirements:</p>\n<ul>\n<li>9+ years of experience in ASIC physical design, with a proven track record in complex SoC or test chip implementations at advanced process nodes.</li>\n<li>Deep expertise in the complete ASIC physical design flow: floor planning, synthesis, P&amp;R, timing closure, IR-drop/EM analysis, LVS/DRC, etc.</li>\n<li>Familiarity with IP integration, test chip methodology, and advanced verification flows.</li>\n<li>Proficiency with state-of-the-art CAD tools such as Design Compiler (DC), PrimeTime (PT), IC Compiler II/FC, ICV, Calibre, RedHawk, and FinFet technologies.</li>\n<li>Experience coordinating complex, cross-functional projects and leading technical execution.</li>\n<li>Authorization to work in the USA.</li>\n</ul>\n<p>Team:</p>\n<p>You&#39;ll join the Test Chip PHY development team within Synopsys&#39;s Silicon IP business. This group is dedicated to integrating and validating Synopsys&#39;s broad portfolio of IP blocks,logic, memory, interfaces, analog, security, and embedded processors,into test chips at the forefront of semiconductor innovation. The team works collaboratively across architecture, RTL, circuit, and covercell disciplines to deliver robust, silicon-proven IP solutions that power next-generation products for global customers.</p>\n<p>Rewards and Benefits:</p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_642c88a4-a92","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/nepean/asic-physical-design-sr-staff-engineer-16724/44408/93743819072","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["ASIC physical design","RTL-to-GDSII flow","Static timing analysis","Physical verification","Design Compiler","PrimeTime","IC Compiler II/FC","Calibre","RedHawk","FinFet technologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:52.721Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Nepean"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"ASIC physical design, RTL-to-GDSII flow, Static timing analysis, Physical verification, Design Compiler, PrimeTime, IC Compiler II/FC, Calibre, RedHawk, FinFet technologies"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7375c418-b8a"},"title":"SOC Engineering, Sr Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p>As a Sr Staff Engineer in SOC Engineering, you will independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs. You will execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets.</p>\n<p>Key Responsibilities:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm)</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimization, and static timing analysis (STA) to meet stringent performance and power targets</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence</li>\n<li>Utilize and optimize Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency</li>\n</ul>\n<p>Key Requirements:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm)</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimization, STA, EMIR, and physical verification</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs</li>\n<li>Exposure to high-frequency design and low-power design methodologies</li>\n</ul>\n<p>Benefits:</p>\n<ul>\n<li>Comprehensive medical and healthcare plans that work for you and your family</li>\n<li>In addition to company holidays, we have ETO and FTO Programs</li>\n<li>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more</li>\n<li>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back</li>\n</ul>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7375c418-b8a","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/bengaluru/soc-engineering-sr-staff-engineer/44408/94212497968","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$120,000 - $180,000 per year","x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimization","static timing analysis (STA)","physical verification","EMIR analysis","timing closure","floor-planning","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime","Python","PERL","TCL","high-frequency design","low-power design methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:12:44.698Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Bengaluru"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimization, static timing analysis (STA), physical verification, EMIR analysis, timing closure, floor-planning, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, Python, PERL, TCL, high-frequency design, low-power design methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":120000,"maxValue":180000,"unitText":"YEAR"}}},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_7c858523-91f"},"title":"SOC Engineering, Staff Engineer","description":"<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.</p>\n<p>We Are:</p>\n<p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are:</p>\n<p>You are a passionate and driven Physical Design Engineer with a strong foundation in RTL2GDSII flows and a proven ability to independently own and deliver complex designs. With at least 5 years of hands-on experience in advanced technology nodes such as 7nm, 5nm, or even 3nm, you thrive in fast-paced, innovative environments and are eager to tackle new technical challenges. Your expertise spans the entire physical design spectrum,from synthesis, place &amp; route, and clock tree synthesis (CTS) to timing optimization, static timing analysis (STA), timing closure, EMIR, and physical verification. You have experience in both block-level and full-chip floor-planning, and you’re adept at navigating timing constraints and closing timing on aggressive schedules. Your toolset includes industry-leading Synopsys solutions like Design Compiler, IC Compiler II, and PrimeTime, allowing you to deliver optimal results for high-frequency, low-power designs.</p>\n<p>Beyond your technical skills, you are a collaborative team player who communicates effectively across global teams, valuing diversity of thought and experience. You are motivated by problem-solving, have a keen analytical mindset, and are always seeking opportunities to automate and optimize workflows using Python, PERL, TCL, or other scripting languages. You take ownership of your work and pride yourself on delivering high-quality, robust solutions that drive organisational success. If you are excited about contributing to leading-edge silicon design and want to make a tangible impact, Synopsys is the place for you.</p>\n<p>What You’ll Be Doing:</p>\n<ul>\n<li>Independently own and drive full RTL2GDSII physical design implementation for advanced process nodes (7nm/5nm/3nm), ensuring successful tape-outs.</li>\n<li>Execute synthesis, place &amp; route, clock tree synthesis (CTS), timing optimisation, and static timing analysis (STA) to meet stringent performance and power targets.</li>\n<li>Perform block-level and full-chip floor-planning, physical verification, EMIR analysis, and timing closure activities.</li>\n<li>Collaborate with cross-functional teams across geographies to resolve complex design challenges and ensure design quality and schedule adherence.</li>\n<li>Utilise and optimise Synopsys EDA tools, including Design Compiler, IC Compiler II, and PrimeTime, to deliver state-of-the-art silicon solutions.</li>\n<li>Develop and maintain automation scripts in Python, PERL, TCL, or other relevant languages to streamline design flows and improve efficiency.</li>\n<li>Contribute to the continuous improvement of design methodologies and best practices, sharing insights and mentoring junior engineers as needed.</li>\n</ul>\n<p>The Impact You Will Have:</p>\n<ul>\n<li>Accelerate the delivery of high-performance, low-power silicon solutions that power next-generation technology platforms worldwide.</li>\n<li>Enable Synopsys customers to achieve first-pass silicon success through robust and innovative physical design implementations.</li>\n<li>Drive technical excellence and best practices within the team, influencing the future direction of physical design methodologies at Synopsys.</li>\n<li>Foster a collaborative and inclusive culture by working seamlessly with global teams and sharing technical expertise.</li>\n<li>Contribute to Synopsys’ leadership in EDA tools adoption, providing valuable feedback to enhance product offerings and customer satisfaction.</li>\n<li>Support strategic customer engagements and help expand Synopsys&#39; presence in the semiconductor ecosystem through successful project outcomes.</li>\n</ul>\n<p>What You’ll Need:</p>\n<ul>\n<li>Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics, Electrical Engineering, or a related field.</li>\n<li>5+ years of relevant experience in physical design, particularly in advanced technology nodes (7nm/5nm/3nm).</li>\n<li>Comprehensive hands-on experience with RTL2GDSII flows, including synthesis, place &amp; route, CTS, timing optimisation, STA, EMIR, and physical verification.</li>\n<li>Proficiency with Synopsys EDA tools such as Design Compiler, IC Compiler II, and PrimeTime.</li>\n<li>Strong scripting and automation skills using Python, PERL, TCL, or similar languages.</li>\n<li>Solid understanding of timing constraints, timing closure, and floor-planning techniques for both block-level and full-chip designs.</li>\n<li>Exposure to high-frequency design and low-power design methodologies.</li>\n</ul>\n<p>Who You Are:</p>\n<ul>\n<li>Proactive, self-motivated, and driven to achieve technical excellence.</li>\n<li>Exceptional problem-solving and analytical skills with a keen attention to detail.</li>\n<li>Excellent communication and interpersonal abilities, comfortable working in diverse and global teams.</li>\n<li>Collaborative team player who values knowledge sharing and mentoring others.</li>\n<li>Adaptable and open to learning new technologies and methodologies in a rapidly evolving field.</li>\n</ul>\n<p>The Team You’ll Be A Part Of:</p>\n<p>You’ll join a world-class team of physical design engineers at Synopsys, dedicated to delivering innovative system design solutions for our global customers. Our team thrives on collaboration, technical excellence, and a shared passion for pushing the boundaries of semiconductor design. Working closely with experts across multiple domains, you will play a key role in empowering customers to achieve their silicon goals while contributing to Synopsys’ leadership in the industry.</p>\n<p>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, colour, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</p>\n<p>Benefits:</p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honoured to work alongside such talented and passionate individuals who choose to make a difference here every day. We’re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<p>Visit Benefits Page</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24-month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<ul>\n<li>Compensation</li>\n</ul>\n<p>Competitive salaries.</p>\n<p>** Benefits vary by country and region - check with your recruiter to confirm</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_7c858523-91f","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/soc-engineering-staff-engineer/44408/92684730800","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["RTL2GDSII flows","synthesis","place & route","clock tree synthesis (CTS)","timing optimisation","static timing analysis (STA)","physical verification","block-level and full-chip floor-planning","EMIR analysis","timing closure","Python","PERL","TCL","Synopsys EDA tools","Design Compiler","IC Compiler II","PrimeTime"],"x-skills-preferred":["high-frequency design","low-power design methodologies","collaboration","problem-solving","analytical skills","communication","interpersonal abilities"],"datePosted":"2026-04-05T13:22:21.047Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"RTL2GDSII flows, synthesis, place & route, clock tree synthesis (CTS), timing optimisation, static timing analysis (STA), physical verification, block-level and full-chip floor-planning, EMIR analysis, timing closure, Python, PERL, TCL, Synopsys EDA tools, Design Compiler, IC Compiler II, PrimeTime, high-frequency design, low-power design methodologies, collaboration, problem-solving, analytical skills, communication, interpersonal abilities"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_106cfbf6-843"},"title":"Physical Design Specialist (PDS)","description":"<p>We&#39;re looking for a Physical Design Specialist (PDS) to join our team. As a PDS, you will support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.</p>\n<p>Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro &amp; Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.</p>\n<p>You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</p>\n<p>As a member of our high-performing Customer Application Services team, you will collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</p>\n<p>Responsibilities:</p>\n<ul>\n<li>Support customers in enjoying Synopsys products, specifically in the areas of Place &amp; Route (physical), Synthesis (logical and physical), STA experience and knowledge.</li>\n<li>Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).</li>\n<li>Collaborate closely with R&amp;D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.</li>\n<li>Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.</li>\n<li>Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.</li>\n</ul>\n<p>Key Qualifications:</p>\n<ul>\n<li>Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)</li>\n<li>RTL to GDSII full flow experience or knowledge is preferable</li>\n<li>Strong interest and understanding of Advanced Node &amp; Design methodologies are required.</li>\n<li>In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.</li>\n<li>Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred</li>\n<li>Excellent verbal and written presentation/communication skills are mandatory.</li>\n<li>Customer sensitivity, the ability to multiplex many issues &amp; set priorities, and the desire to help customers exploit new technologies are essential for success in the position.</li>\n</ul>\n<p>Preferred Experience:</p>\n<ul>\n<li>BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.</li>\n<li>Tool knowledge expected: Back end P&amp;R tools (Fusion Compiler, ICC2, Innovus)</li>\n<li>Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),</li>\n<li>Tool knowledge (preferred): STA (Primetime, Tempus)</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_106cfbf6-843","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/hyderabad/application-engineering-principal-engineer/44408/92840962656","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Place & Route (physical)","Synthesis (logical and physical)","STA experience and knowledge","Macro & Standard Cell Placement","Clock Tree Synthesis","Routing","Advanced Timing Optimization techniques","Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2)"],"x-skills-preferred":["RTL to GDSII full flow experience","Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis)","Clock Tree Synthesis methodologies like H-Tree, MS-CTS"],"datePosted":"2026-04-05T13:22:15.432Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Hyderabad"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge, Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques, Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2), RTL to GDSII full flow experience, Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis), Clock Tree Synthesis methodologies like H-Tree, MS-CTS"},{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_ea6a34b3-c1d"},"title":"Staff Memory Layout Engineer","description":"<p>We are seeking a Staff Memory Layout Engineer to join our team. As a Staff Memory Layout Engineer, you will be responsible for leading the physical layout design of advanced memory IP (SRAM, ROM, eDRAM, etc.) at cell, array, and peripheral levels.</p>\n<p><strong>What you&#39;ll do</strong></p>\n<ul>\n<li>Lead the physical layout design of advanced memory IP (SRAM, ROM, eDRAM, etc.) at cell, array, and peripheral levels</li>\n<li>Ensure compliance with foundry process design rules (DRC/LVS) and memory-specific constraints</li>\n</ul>\n<p><strong>What you need</strong></p>\n<ul>\n<li>Bachelor&#39;s or Master&#39;s degree in Electronics Engineering, Telecommunication, Physics, or related fields</li>\n<li>Minimum of 5 years of experience in layout design</li>\n</ul>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_ea6a34b3-c1d","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/da-nang/staff-memory-layout-engineer-in-da-nang/44408/91391710096","x-work-arrangement":"onsite","x-experience-level":"staff","x-job-type":"employee","x-salary-range":null,"x-skills-required":["layout design","foundry process design rules","memory-specific constraints"],"x-skills-preferred":["Custom Compiler","IC Compiler","Virtuoso"],"datePosted":"2026-03-06T07:23:16.436Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Da Nang"}},"occupationalCategory":"Engineering","industry":"Technology","skills":"layout design, foundry process design rules, memory-specific constraints, Custom Compiler, IC Compiler, Virtuoso"}]}