We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.

Key Responsibilities:

• Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes
• Driving timing closure efforts, especially above ~2GHz
• Resolving complex challenges related to mixed signal and macro IP integration
• Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements
• Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams
• Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects
• Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation

Requirements:

• Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications
• Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)
• Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration
• Strong analytical and problem-solving skills, with a track record of resolving complex technical issues
• Ability to independently lead project tasks, mentor junior team members, and work collaboratively

Benefits:

• Comprehensive medical and healthcare plans
• Time away from work for vacation, sick leave, and family care
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP (Employee Stock Purchase Plan)
• Retirement plans
• Competitive salaries

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