We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are: You are an accomplished verification engineer with a passion for excellence and a track record of delivering robust, high-quality IP solutions. You thrive in a fast-paced, dynamic environment and are excited by the opportunity to work on next-generation connectivity protocols that power commercial, enterprise, and automotive applications. With a solid foundation in Electrical/Electronics Engineering (BSEE with 5+ years or MSEE with 3+ years of relevant experience), you bring deep expertise in System Verilog and industry-standard verification methodologies such as UVM/OVM/VMM. Your hands-on experience developing HVL-based test environments and extracting meaningful verification metrics sets you apart as a technical leader.

You are a collaborative team player who values knowledge sharing and actively contributes to a culture of continuous improvement. Your familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB allows you to quickly ramp up on new projects and deliver results. You bring a strong analytical mindset, exceptional debugging skills, and a drive to meet and exceed quality metrics. Experienced with scripting languages like Perl, TCL, and Python, you automate processes for efficiency and scalability. Your strong communication skills, initiative, and global perspective enable you to work effectively with cross-functional and multi-site teams. Above all, you are a lifelong learner who embraces challenges, adapts to new technologies, and is committed to shaping the future of silicon design.

What You’ll Be Doing: Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies. Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements. Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities. Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics. Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure. Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity. Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

The Impact You Will Have: Ensure the delivery of high-quality, robust IP cores that power critical applications in commercial, enterprise, and automotive markets. Drive innovation in verification methodologies, setting new standards for efficiency and coverage. Enhance time-to-market by identifying and resolving design and verification issues early in the development cycle. Strengthen Synopsys’ reputation as a leader in silicon IP and verification through technical excellence and customer focus. Mentor and support junior engineers, fostering a culture of learning and continuous improvement. Contribute to the success of global, multi-site R&D teams by providing expertise and driving cross-functional collaboration.

What You’ll Need: BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification. Expertise in developing HVL (System Verilog)-based verification environments and testbenches. Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools. Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable. Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB. Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus. Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Who You Are: Analytical thinker with strong problem-solving and debugging skills. Excellent verbal and written communication abilities. Team player who thrives in collaborative, multi-site environments. Proactive, self-motivated, and able to take initiative on challenging projects. Detail-oriented, quality-focused, and driven by a desire to excel. Adaptable and eager to continuously learn and apply new technologies.

The Team You’ll Be A Part Of: You will join the Solutions Group’s DesignWare IP Verification R&D team, a highly skilled and diverse group of engineers dedicated to delivering world-class IP cores for next-generation connectivity. The team operates in a collaborative, multi-site environment, leveraging global expertise to solve complex verification challenges. Together, you will drive innovation, share knowledge, and uphold Synopsys’ reputation for technical leadership and excellence.

Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Benefits: At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

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They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

These engineers play a crucial role in advancing technology and enabling innovations in various industries.

We are seeking a highly skilled and experienced ASIC verification professional to lead technical teams and drive excellence in digital design.

As a Sr Staff Engineer - DDR, you will be responsible for technically leading and driving ownership of critical areas of verification alongside a team of talented verification engineers.

You will specify, design, and implement state-of-the-art verification environments for the DesignWare family of synthesizable cores.

You will perform verification tasks for IP cores, working closely with RTL designers and architects to ensure functional correctness.

You will develop and implement advanced test plans and test environments at both unit and system levels.

You will code and debug test cases, including the creation of complex checkers and assertions using System Verilog/UVM.

You will extract and review functional coverage (FC) and code coverage metrics to ensure quality metric goals are met.

You will manage regressions and contribute to the continuous improvement of verification strategies and test environments.

This role requires a deep understanding of verification methodologies, serial interface protocols, and the intricacies of IP core development.

You should have demonstrated experience in technically leading a team for DDR IP projects, with a track record of successful collaboration and stakeholder management.

You should have proven expertise in developing HVL (System Verilog/UVM) based test environments for complex ASIC designs.

You should have advanced skills in developing and implementing rigorous test plans, checkers, and assertions.

You should have strong proficiency in extracting and analyzing verification metrics such as functional coverage and code coverage.

You should have experience with serial interface protocols and IP design/verification processes; knowledge of DDR/LPDDR is highly desirable.

You should have hands-on experience in owning end-to-end verification deliverables for IPs, including planning, execution, DV metrics closure, and review/signoff.

You will join the DesignWare IP Verification R&D team, a group of talented and passionate engineers committed to advancing Synopsys' leadership in semiconductor IP.

The team focuses on delivering world-class verification solutions for a broad portfolio of synthesizable IP cores, leveraging the latest methodologies and technologies to ensure our products meet the most rigorous quality and performance standards.

Collaboration, innovation, and a drive for excellence define our culture.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.

Our total rewards include both monetary and non-monetary offerings.

Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are a driven and curious engineering professional, passionate about tackling complex technical challenges and eager to make a real difference in the semiconductor industry. You thrive in collaborative, diverse environments and are energized by working alongside global experts to solve high-value problems. You are committed to continuous learning and growth, staying ahead of the curve in verification methodologies, HDL/HVL technologies, and dynamic simulation.

Collaborate with customers to understand their verification challenges and provide tailored technical solutions using Synopsys Verification Platform. Support customer projects throughout their tapeout schedules, ensuring timely resolution of technical issues and successful project outcomes. Deliver technical presentations, workshops, and training sessions on Synopsys EDA tools, methodologies, and best practices.

Enable customers to optimize and verify chips for power, cost, and performance—accelerating their time-to-market. Build strong, collaborative relationships with customers, fostering trust and loyalty through expert support and innovation. Drive adoption of Synopsys Verification Platform, contributing to company growth and industry leadership.

Master’s degree in Electronics, or Bachelor’s degree in Electronics with 1-2 years of relevant experience. Solid understanding of digital design, HDLs (Verilog, VHDL), and System Verilog. Experience with dynamic simulation verification, including methodologies, debug, low power, and coverage. Familiarity with Synopsys EDA tools (VCS, Verdi) is a plus. Proficiency in UNIX environments and scripting languages such as Tcl, with the ability to automate and optimize workflows.

Collaborative team player who values diversity and inclusion. Detail-oriented, organized, and able to manage multiple priorities effectively. Innovative thinker with a proactive, results-driven mindset. Motivated, self-organized, and open to travel as required. Strong interpersonal and social communication skills, fostering positive relationships with colleagues and clients. Adaptable and eager to learn, embracing new technologies and methodologies.

You’ll be part of the Customer Success Group, a collaborative and diverse team dedicated to building strong partnerships with market leaders and innovators. The team’s core mission is to enable customers to solve high-value problems through advanced verification solutions and continuous technical support. Working closely with domain experts across global locations, you’ll develop deep expertise in Synopsys Verification Platform and play a key role in helping customers achieve their design goals efficiently and effectively.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
• Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
• Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.

What you need

• BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
• Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
• Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.

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What you'll do

Specifying, designing, and implementing state-of-the-art verification environments for the DesignWare family of synthesizable cores.

Performing verification tasks for IP cores, including test planning and environment coding at both unit and system levels.

Developing and implementing test cases, debugging, functional coverage coding, and testing to meet quality metric goals.

Managing regression and ensuring adherence to verification methodologies.

Collaborating closely with RTL designers and a global team of verification engineers.

Working on next-generation connectivity protocols for commercial, enterprise, and automotive applications.

What you need

BSEE in Electrical Engineering with 12+ years of relevant experience or MSEE with 10+ years of relevant experience.

Experience in architecting verification environments for complex serial protocols.

Proficiency in HVL (System Verilog) and industry-standard simulators such as VCS, NC, and MTI.

Expertise in verification methodologies such as VMM, OVM, and UVM.

Knowledge of protocols like MIPI-I3C, UFS, Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, and USB.

Familiarity with Verilog and scripting languages such as Perl, TCL, and Python.

Experience with IP design and verification processes, including VIP development.

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