You are a highly skilled engineer with deep expertise in analog design and memory compiler flow. You excel in a dynamic environment, leveraging your proficiency in Circuit design, Memory architecture, Python, and Hspice to deliver innovative, high-quality solutions. Your strategic mindset and technical acumen allow you to solve complex engineering challenges and collaborate effectively across multiple functional areas.

Key Responsibilities:

Designing, developing, and evaluating physical IP - Memory compilers (SRAM/RF/ROM/TCAM etc.). Applying your expertise in Circuit design, Memory architecture, Python, and Hspice to optimize workflows and enhance design efficiency. Collaborating with cross-functional teams to align project deliverables with business objectives. Contributing to the technical direction and problem-solving efforts within the engineering group. Sharing knowledge and supporting the professional growth of team members through technical mentorship.

Impact:

Advance our product portfolio with innovative solutions addressing market demands. Improve the efficiency and effectiveness of engineering development workflows. Solve complex engineering challenges, contributing to successful project outcomes. Support the growth and technical development of colleagues through guidance and collaboration. Contribute to Synopsys' success by delivering high-quality products on schedule. Help foster a culture of innovation and continuous improvement within the engineering team.

Requirements:

Bachelor's or master's degree in Electrical Engineering, Computer Science, or a related field. Significant experience in analog design and memory compiler flow. Proficiency in Python and Hspice. Strong problem-solving and technical skills. Ability to work collaboratively and communicate effectively within and across teams.

Team:

You will be part of a dynamic and innovative engineering team at the forefront of high-performance silicon chip and software development. Our team relentlessly pushes technology boundaries, delivering solutions that drive the Era of Pervasive Intelligence. We collaborate closely to ensure our products meet the highest standards of quality and performance.

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

As a UCIe Analog Design Senior Engineer at Synopsys, you will design circuit for Analog IPs like High Speed IOs, LCDL, Bandgap, High Speed macros for high speed PHY, Clock trees, Calibration circuits...

You will analyze and verify to make sure design meet all requirements of functionality, performance, area and reliability.

You will work closely with layout engineers to make sure layout quality. Perform post layout verifications.

You will perform design characterizations, functionality checks, EMIR analysis, Co-simulations for Logic-Analog full chip operations.

You will design analysis and solve problems of noise, margin, signal integrity, power integrity.

You will complete all design quality checks and data quality checks

You will do design reviews across global team

You will work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.

You will train for fresh engineers and interns

The ideal candidate will have a BS/MS in Electronics Engineering, Electromechanics, Telecommunications.

They should have 0-3 years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.

They should have solid knowledge of CMOS Analog design knowledge and techniques

They should have solid skill with circuit design tools: SNSP Custom Designer, Cadence Virtuoso

They should have solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim...

They should have good understanding of layout effects on circuit performance.

They should have experienced with writing design review presentations and circuit verification reports

They should have good English communication both verbally and in writing

They should be a great team player, willing to support others.

They should be highly responsible, result oriented.

They should be self-motivated and highly enthusiasm in technology and solving problems

Leadership skill and experience is a plus

Familiar with high speed analog designs, IO designs, PLL/DLL is a plus

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This role involves defining, implementing, and tracking comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.

Key responsibilities include building, enhancing, and maintaining top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

The ideal candidate will have a strong foundational understanding of analog circuits, expertise with AMS tools such as HSPICE, XA, Custom Sim, VCS, and proficiency with System Verilog/UVM.

As a member of the Synopsys IPG Co-Simulation (COSIM) team, you will collaborate closely with mixed-signal designers, modeling engineers, and system architects across global Synopsys teams to deliver best-in-class IP.

In this role, you will enable the successful verification and deployment of high-performance SERDES and mixed-signal IP in leading-edge SoCs worldwide.

Synopsys is a comprehensive range of health, wellness, and financial benefits to cater to your needs.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work.

We consider all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

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Your contributions will drive innovation in SRAM IP design, maintaining Synopsys’s leadership in memory technology. You will enhance product performance and reliability for global semiconductor customers. You will support the delivery of best-in-class SRAM compilers used in high-performance silicon chips. You will strengthen quality assurance processes, ensuring robust and scalable designs. You will accelerate time-to-market for new memory IP solutions through efficient verification and debug activities. You will contribute to the development of advanced memory architectures, impacting next-generation electronic devices.

To be successful in this role, you will need a Master’s degree in Electrical/Electronic Engineering or a related field. You will have 3–7+ years of hands-on experience in SRAM circuit design. You will have prior understanding of CMOS-based block level circuit design and SRAM architectures. You will have experience with SP/2P/ROM variety design and SRAM bitcell analysis. You will be proficient in digital circuit design and VLSI process concepts. You will have familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell. You will have experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR. Post-silicon debug experience is a plus.

You will be an analytical thinker with strong problem-solving skills. You will be curious and eager to learn new technologies and concepts. You will be detail-oriented and committed to delivering high-quality results. You will be a collaborative team player with effective communication skills. You will be adaptable and able to manage multiple tasks in a fast-paced environment. You will be self-motivated and resourceful in overcoming technical challenges.

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You enjoy solving complex problems and are not afraid to explore new methods and technologies. You bring a strong analytical mindset, excellent problem-solving skills, and a willingness to learn from both successes and setbacks. You value diversity and inclusion, recognizing that the best solutions come from teams with varied perspectives. You take pride in your work, communicate effectively, and are motivated to deliver high-quality results. Whether you are fresh out of graduate school or have a few years of hands-on experience, you are ready to take on new challenges and contribute to innovations that power the next generation of intelligent devices.

What You’ll Be Doing:

• Designing and verifying the robustness of SRAM integrated circuits, ensuring optimal performance and reliability.
• Developing and enhancing SRAM compilers, including GDS and netlist tiling for efficient memory layout and integration.
• Characterizing SRAM modules for timing, power, and functional parameters to meet stringent specifications.
• Analyzing and developing SRAM bitcell design criteria, supporting a wide range of memory architectures.
• Utilizing EDA tools (XA, Hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
• Collaborating with cross-functional teams to resolve post-silicon issues and continuously improve memory IP quality.
• Exploring new SRAM architectures including SP, 2P, and ROM varieties, contributing to innovation in IP solutions.

The Impact You Will Have:

• Advance the capabilities of Synopsys’s SRAM IP, strengthening its position as an industry leader.
• Deliver high-performance, reliable memory solutions that enable next-generation chips for global customers.
• Drive innovation by creating robust, scalable, and energy-efficient SRAM designs.
• Enhance the efficiency and productivity of the design team through automation and process improvements.
• Support successful silicon tapeouts and post-silicon validation, ensuring product excellence.
• Contribute to a collaborative and inclusive team culture that values knowledge sharing and continuous learning.

What You’ll Need:

• Master’s degree in Electrical/Electronic Engineering or a related field.
• Strong understanding of CMOS-based block level circuit design and SRAM architectures.
• Solid grasp of digital circuit design and VLSI process concepts.
• Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell for workflow automation.
• Experience 3~10 years in SRAM circuit design, bitcell analysis, and design criteria development.
• Knowledge of SP/2P/ROM variety designs and post-silicon debug processes is a plus.
• Proficiency with EDA tools including XA, Hspice, Verilog, Starrc, and EMIR for simulation and verification.

Who You Are:

• Innovative thinker with a strong desire to learn and explore new technologies.
• Detail-oriented and analytical, capable of tackling complex technical challenges.
• Collaborative team player who values diverse perspectives and open communication.
• Effective communicator able to present ideas clearly and work across global teams.
• Resilient and adaptable, able to thrive in a fast-paced, ever-evolving environment.
• Proactive problem solver who takes ownership of projects and drives results.

The Team You’ll Be A Part Of:

You will join Synopsys’s world-class SRAM circuit and compiler design department, the largest of its kind globally. Our team is at the forefront of memory IP solutions, working collaboratively to deliver robust, high-performance SRAM products for a diverse range of applications. We foster a culture of innovation, knowledge sharing, and continuous improvement, empowering each member to contribute to the advancement of cutting-edge technologies in semiconductor design.

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What you'll do

• Responsible for modeling(IBIS, AMI,CMM, CPM, CTM), simulating, analyzing signal and power integrity (SIPI), troubleshooting, and reviewing interfaces interconnect.
• Performs, verifies, and documents interface SIPI analysis outcome as part of global chip design team.
• Carry out experiments to validate modeling and methodologies.
• Develop and document signal and power integrity requirements and flows for internal and external customer use.

What you need

• Possesses excellent communication skills, both verbal and written.
• Familiarity with both Windows and Linux operating system is required.
• An understanding of basic circuit and transmission line theory is essential, as is familiarity with and a working knowledge of concurrent time and frequency-domain methods of analysis and characterization.
• Knowledge on interface such as UCIE is a plus, though DDR, HBM, PCIe (e.g. gen 6/5), Ethernet, SATA, for example, can be leveraged.
• Some experience in programming languages such as Python, TCL and Matlab is desired.
• A working knowledge of circuit simulation tools such as Synopsys HSPICE is required. Experience with Redhawk, Totem, Ansys AEDT, Keysight ADS, etc. is a plus.
• Practical experience with package and pcb design 3D electro-magnetic field solvers such as Ansys SiWave/HFSS, with proven ability to create models of usable bandwidth up-to 20GHz is preferred.
• Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills.
• Bachelor's or Master's degree in Electrical or Electronics Engineering, with a minimum of 6 years of relevant experience in supporting interface IP product development (preferably DDR), system integration and Signal and Power verifications flow/methodologies.

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What you'll do

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.

What you need

• Bachelor's or master's degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits (op-amps, bandgaps, PLLs, ADCs, TX/RX components, etc.).
• Experience with AMS tools such as HSPICE, XA, Custom Sim, VCS, and scripting languages like Python, Perl, and UNIX shell.

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What you'll do

• Driving innovation in high-speed interface DDR IP products, facilitating the development of cutting-edge solutions and SI/PI methodologies.
• Enhancing customer satisfaction by providing expert SI/PI support and guidance for interface IP integration at both pre- and post-sales stages.

What you need

• Proven expertise in signal and power integrity for high-speed interfaces, including mixed-signal design and off-chip system signaling.

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