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YubHub-native raw fields carry `x-` prefix.","jobs":[{"@context":"https://schema.org","@type":"JobPosting","identifier":{"@type":"PropertyValue","name":"YubHub","value":"job_8142c2c7-bfb"},"title":"Principal STA Engineer","description":"<p><strong>Overview</strong></p>\n<p>Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.</p>\n<p><strong>Job Description</strong></p>\n<p>As a Principal STA Engineer, you will be responsible for owning full-chip and block-level STA sign-off across all PVT corners and operational modes. You will drive timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.</p>\n<p><strong>Responsibilities</strong></p>\n<ul>\n<li>Owning full-chip and block-level STA sign-off across all PVT corners and operational modes.</li>\n<li>Driving timing closure from synthesis through place-and-route to tapeout, ensuring first-pass silicon success.</li>\n<li>Analyzing and resolving setup/hold violations, noise, signal integrity (SI), OCV, and derates.</li>\n<li>Defining and validating timing margins, guard-bands, and sign-off criteria for advanced node designs.</li>\n<li>Managing complexities at 7nm, 5nm, and 3nm nodes, including variation-aware timing (AOCV/POCV), crosstalk, and clock distribution.</li>\n<li>Developing and reviewing SDC constraints (clocks, IO delays, exceptions) for MCMM designs.</li>\n<li>Building scalable timing methodologies and driving constraint validation and consistency across teams.</li>\n<li>Utilizing STA tools (Primetime, Tempus) and scripting (Tcl/Python) for automation and flow efficiency.</li>\n<li>Leading timing reviews and sign-off meetings with cross-functional stakeholders.</li>\n</ul>\n<p><strong>The Impact You Will Have</strong></p>\n<ul>\n<li>Ensuring successful tapeouts and robust silicon performance at advanced technology nodes.</li>\n<li>Driving innovation in timing sign-off methodologies, influencing industry standards and best practices.</li>\n<li>Reducing time-to-market by achieving efficient timing closure and minimizing design iterations.</li>\n<li>Enhancing cross-functional collaboration and knowledge sharing within Synopsys engineering teams.</li>\n<li>Mentoring and developing junior engineers, building a stronger and more resilient team.</li>\n<li>Contributing to architectural decisions that improve timing convergence and silicon reliability.</li>\n<li>Streamlining timing analysis workflows through automation, improving productivity and accuracy.</li>\n</ul>\n<p><strong>What You’ll Need</strong></p>\n<ul>\n<li>B.Eng, or MS in Electrical Engineering or a related field.</li>\n<li>10–15+ years of experience in STA and timing sign-off for SoCs.</li>\n<li>Proven record of successful tapeouts in advanced nodes (7nm, 5nm, 3nm).</li>\n<li>Expertise in STA tools (Primetime, Tempus) and scripting languages (Tcl, Python, Perl).</li>\n<li>Deep understanding of EM/IR and reliability impacts on timing.</li>\n<li>Experience with full-chip integration and hierarchical STA methodologies.</li>\n<li>Ability to develop scalable timing methodologies for MCMM designs.</li>\n</ul>\n<p><strong>Who You Are</strong></p>\n<ul>\n<li>Technical leader and mentor, passionate about knowledge sharing.</li>\n<li>Collaborative communicator, able to lead cross-functional teams and drive consensus.</li>\n<li>Detail-oriented and analytical, with a relentless focus on quality and accuracy.</li>\n<li>Innovative thinker, eager to explore new approaches and technologies.</li>\n<li>Adaptable, capable of navigating fast-paced and evolving engineering environments.</li>\n<li>Confident decision-maker, able to advocate for best practices and influence architectural choices.</li>\n</ul>\n<p><strong>The Team You’ll Be A Part Of</strong></p>\n<p>You will join a dynamic, highly skilled SOC engineering team dedicated to delivering world-class silicon solutions at the forefront of semiconductor technology.</p>\n<p><strong>Rewards and Benefits</strong></p>\n<p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.</p>\n<p><strong>Benefits</strong></p>\n<p>At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We&#39;re proud to provide the comprehensive benefits and rewards that our team truly deserves.</p>\n<ul>\n<li>Health &amp; Wellness</li>\n</ul>\n<p>Comprehensive medical and healthcare plans that work for you and your family.</p>\n<ul>\n<li>Time Away</li>\n</ul>\n<p>In addition to company holidays, we have ETO and FTO Programs.</p>\n<ul>\n<li>Family Support</li>\n</ul>\n<p>Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.</p>\n<ul>\n<li>ESPP</li>\n</ul>\n<p>Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.</p>\n<ul>\n<li>Retirement Plans</li>\n</ul>\n<p>Save for your future with our retirement plans that vary by region and country.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_8142c2c7-bfb","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/austin/principal-sta-engineer/44408/93189758160","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":"$170,000-$255,000","x-skills-required":["STA","timing sign-off","SoCs","Primetime","Tempus","Tcl","Python","Perl","EM/IR","reliability impacts on timing","full-chip integration","hierarchical STA methodologies"],"x-skills-preferred":[],"datePosted":"2026-04-05T13:22:05.689Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Austin"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"STA, timing sign-off, SoCs, Primetime, Tempus, Tcl, Python, Perl, EM/IR, reliability impacts on timing, full-chip integration, hierarchical STA methodologies","baseSalary":{"@type":"MonetaryAmount","currency":"USD","value":{"@type":"QuantitativeValue","minValue":170000,"maxValue":255000,"unitText":"YEAR"}}}]}