As a Senior Engineer in the R&D department, you will be responsible for developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI. You will implement designs in C++, RTL, and SystemVerilog-DPIs, and collaborate with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments. You will also create and optimize use models and applications for various emulation projects, conduct thorough verification and validation processes to ensure the highest quality of emulation models, and provide technical guidance and mentorship to junior team members when necessary.

Key responsibilities include:

• Developing and deploying emulation models for Zebu, focusing on bus protocols like PCIe, USB, CSI, and DSI.
• Implementing designs in C++, RTL, and SystemVerilog-DPIs.
• Collaborating with cross-functional teams to ensure seamless SoC bring-up and software development in pre-silicon environments.
• Creating and optimizing use models and applications for various emulation projects.
• Conducting thorough verification and validation processes to ensure the highest quality of emulation models.
• Providing technical guidance and mentorship to junior team members when necessary.

As a member of the Emulation Transactor Development Team, you will work closely with various teams across the organization to ensure the highest quality in our products. Our collaborative and inclusive environment encourages innovation, continuous learning, and personal growth.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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You are an experienced ASIC Digital Signoff Engineer with a deep passion for developing cutting-edge technology and direct hands-on experience with EM and IR flows. With over 10 years of hands-on experience, you have honed your skills in high-speed digital IP cores and/or SOCs development. You have a solid understanding of digital design flows and deep expertise in Static Timing Analysis (STA), Power Analysis, and EM/IR for advanced node designs.

Your technical expertise is complemented by your ability to foster cross-functional collaboration, driving innovation and effective communication across global teams. Your analytical mind and problem-solving skills enable you to tackle complex challenges and deliver high-quality results. You are known for your clear and concise documentation, and your familiarity with Synopsys tools and high-speed interface protocols is a significant advantage.

You will develop and deploy advanced node signoff methodologies for cutting-edge IP designs targeting different foundries. You will work with leading edge designs and teams to drive the industry best PPA for IP designs. You will evaluate and exercise various aspects of the development flow which include signoff timing, power, physical verification, EM/IR analysis, and ECO's.

You will develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials. You will work as a liaison between EDAG tool and IP design teams. You will continuously improve and refine design processes to enhance efficiency and performance.

You will have a BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs. You will have knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions. You will have direct hands-on experience with enabling advanced node Redhawk SC EM and IR flows.

You will have the ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results. You will have good analysis, debugging, and problem-solving skills. You will have solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

You will have familiarity with other Synopsys tools such as StarRC and ICV is a plus. You will have working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

You will drive innovation in high-speed digital IP core and Subsystem development. You will enhance the efficiency and effectiveness of our design and verification processes. You will contribute to the development of state-of-the-art technology that powers the next generation of intelligent systems. You will ensure the highest quality standards in the design and implementation of our products.

You will facilitate seamless collaboration across global teams, fostering a culture of innovation and excellence. You will support the continuous improvement of our design methodologies and tools, staying at the forefront of industry advancements.

You will join the Interface IP Digital Design Methodology team, working with global teams to define best practice ASIC design standards and flows. This team is dedicated to supporting IP development teams and is involved with next-generation SerDes and Memory interface controllers, PHYs, and subsystems.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

• Developing and writing high-quality user documentation for a variety of Digital and Mixed Signal IPs, including USB, PCIe, Ethernet, DDR, HDMI, and MIPI.
• Planning, organizing, and editing technical specifications, engineering schematics, application notes, and user guides to ensure clarity and usability.

What you need

• Bachelor’s or Master’s degree in Electronics, Science, Hardware, Computing, Software, Physics, Mathematics, Engineering, or a related technical discipline.
• 3-7 years of technical writing experience in the software or hardware industry, with proven ability to deliver high-quality documentation.

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What you'll do

Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.

Work with leading edge designs and teams to drive the industry best PPA for IP designs.

Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.

Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.

Work as a liaison between EDAG tool and IP design teams.

Continuously improve and refine design processes to enhance efficiency and performance.

What you need

BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.

Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.

Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.

Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.

Good analysis, debugging, and problem-solving skills.

Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.

Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

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