Your responsibilities will include:

• Rapidly develop, test, and implement FPGA designs using Xilinx SoC/FPGA.
• Integrate third-party vendors IP, as necessary.
• Work with third-party developers to ensure timely product success
• Perform digital circuit design, VHDL/Verilog coding, synthesis, place and route, timing closure, simulation, and verification.
• Participate in entire design life cycle: from requirements and concept, through design and hand on testing/board bring up.
• Implement a variety of signal types such as high speed comms (ethernet, serial), signal processing (analog, digital).
• Ensure designs meet all relevant safety and performance standards, with traceability back to top-level system requirements, as necessary.
• Investigate and resolve bugs found during hand on testing (at HDL level and system level).

Required qualifications include:

• 5 years of experience preferred in FPGA/HDL hardware design. Experience with Xilinx SoC (Versal) is highly preferred.
• Familiarity with design software like Vivado (preferred), ModelSim, or Quartus.
• Proficient in VHDL and/or Verilog.
• Ability to work in a fast-paced, challenging environment.
• Excellent problem-solving and organizational skills.
• Strong communication and teamwork skills.
• Experience in SoC hardware bring-up, preferably on ARM-based systems.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Preferred qualifications include:

• Working knowledge of designing for safety-critical functions.
• FPGA interfaces and high speed busses.
• Experience with systems on a Chip (SoC).
• Low-level firmware (C/C++) development for bring-up and test.
• Experience writing HDL for Space applications.

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You will be responsible for designing and optimizing accelerated verification tools using massive parallelism and GPU technologies, implementing and troubleshooting advanced graph algorithms to manage complex hardware designs, developing GPU kernels (CUDA/HIP/DPC++) to reduce simulation runtimes, leveraging multi-threaded programming (OpenMP/TBB) to maximize throughput, and debugging functionality and performance of compiler enhancements and optimizations.

Your impact will be accelerating customer chip development cycles and enabling next-generation silicon design, driving innovation in GPU-powered algorithms, and empowering engineering teams to achieve faster RTL sign-off.

To succeed in this role, you will need proficiency in C/C++ and performance profiling, knowledge of GPU computing (CUDA/HIP/DPC++) and parallel memory models, experience with multi-threaded programming (OpenMP, TBB), knowledge in HDL (SystemVerilog/VHDL) and compiler design, an AI-First Mindset: proficiency in using modern AI-assisted coding tools like Cursor or Claude Code to accelerate development cycles and maintain high code quality, and a Growth Mindset: we welcome candidates with HPC and algorithm expertise who have an interest in mastering the hardware verification domain.

Desirable skills include experience implementing high-performance graph algorithms on GPU and multicore architectures, familiarity with distributed computing frameworks and memory-efficient data structures.

Education and experience requirements include a BS in CS/EE or related field with 5+ years of experience, a MS in CS/EE or related field with 3+ years of experience, or a PhD in CS/EE with 0-1 years of experience.

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You are an accomplished engineer with a passion for system-level design and a proven track record in virtual prototyping for complex SoCs, MCUs, or ECUs. With at least 3 years of experience and an educational background in Computer Science or Electronics (BE/B.Tech/M.Tech), you thrive in dynamic environments where technological challenges are the norm.

Key responsibilities:

• Designing and developing virtual prototypes (simulation models) for advanced SoC, MCU, and ECU platforms across automotive, datacentre, AI, and mobile applications.
• Modeling, integrating, and testing various peripherals using SystemC-based platform modeling frameworks.
• Collaborating with stakeholders to define IP modeling requirements and creating ESL (Electronic System Level) model specifications.
• Driving effective closure of technical issues, ensuring high-quality deliverables and alignment with project goals.
• Guiding and mentoring junior engineers and consultants in system-level platform creation, validation, and software bring-up activities.
• Engaging in early software development and testing use cases, including bringing up Linux, Android, AutoSAR, and embedded software applications.
• Contributing to the continuous improvement of virtual prototyping methodologies, tools, and workflows.

Requirements:

• Strong proficiency in C/C++ programming languages.
• 3+ years of industry experience in similar domain
• Extensive experience in modeling and integrating SoC peripherals using C/C++, SystemC, or HDL.
• Solid problem-solving skills with the ability to analyze and resolve complex technical challenges.
• Experience developing applications in assembly or higher-level languages.
• Understanding of SoC architectures and serial bus protocols such as CAN, LIN, SPI, and I2C.
• Hands-on experience with Synopsys Virtualizer tool (preferred).
• Knowledge of multi-core platform development and GitHub Copilot/Curson-assisted flows (preferred).

Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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