You are a dedicated and meticulous Layout Design Engineer with a passion for semiconductor technology. Your expertise lies in the intricate world of IC layout, and you thrive in environments that demand precision, creativity, and innovation.

Designing and developing standard cell layouts, ranging from simple (INV, ND, NR) to complex cells (Level Shifters, Flip Flops, Multi-bit combinational, Multi-bit Flip Flop cells) within the Logic Libraries IP team.

Developing cells across planar, CMOS, FinFet, GAA, uni-directional and multi-directional routing technologies, adapting to both native and cutting-edge platforms.

Applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries.

Collaborating with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

Conducting design reviews and offering constructive feedback to enhance quality and performance.

Utilizing Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

Accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions.

Ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products.

Enhancing productivity and efficiency through workflow automation and quality assurance initiatives.

Driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA.

Fostering collaboration across global teams, leading to improved methodologies and best practices.

Maintaining the highest standards of quality, compliance, and performance in every design delivered.

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As a Layout Design Engineer, you will be designing and developing standard cell layouts, ranging from simple to complex cells, within the Logic Libraries IP team. You will also be applying comprehensive sign-off checks to optimize manufacturability, performance, and yield across multiple foundries.

Key responsibilities include:

• Designing and developing standard cell layouts
• Applying comprehensive sign-off checks
• Collaborating with global teams to resolve methodology issues and implement optimized layout designs
• Conducting design reviews and offering constructive feedback to enhance quality and performance

You will join a dynamic, innovative, high-performing, globally distributed Logic Library layout design team focused on creating world-class IP solutions. The team is dedicated to excellence and continuous improvement, working collaboratively to achieve the organization's goals.

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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Your responsibilities will include applying comprehensive sign-off checks (DRC/LVS/ERC/ANT/DFM) to optimize manufacturability, performance, and yield across multiple foundries. You will collaborate with global teams, circuit design, CAD, and PD teams to resolve methodology issues and implement optimized layout designs.

You will conduct design reviews and offer constructive feedback to enhance quality and performance. You will utilize Unix/Shell/Python/TCL/ICV scripting to automate design workflows, QA checks, checklist enforcement, and quality metrics generation.

The impact you will have includes accelerating the creation and optimization of high-performance logic library IP for next-generation silicon solutions, ensuring robust manufacturability and yield, contributing to the reliability and success of Synopsys' IP products, enhancing productivity and efficiency through workflow automation and quality assurance initiatives, driving innovation by implementing advanced layout techniques for emerging technologies like FinFet and GAA, fostering collaboration across global teams, leading to improved methodologies and best practices, and maintaining the highest standards of quality, compliance, and performance in every design delivered.

To succeed in this role, you will need a BTech/MTech in Electrical Engineering, Electronics, or related field, with 5+ years of relevant experience in IC layout design, preferably in standard cell libraries. You will require proficiency with Synopsys Custom Compiler, Virtuoso, Innovus/ICC2, and ICV/Calibre (DRC/LVS/DFM), hands-on experience with TSMC, Samsung, UMC, and GlobalFoundries PDKs, strong scripting skills in Python, Tcl, Perl, SKILL, ICV, and shell scripting, solid understanding of sign-off flow, waiver handling, and quality tracking, excellent written and spoken English for technical communication, deep knowledge of CMOS, DPT, EM/IR, ESD/latch-up, noise, and digital layout fundamentals, and ability to work independently and collaborate effectively across teams.

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