Your responsibilities will include:

• Architecting and optimizing high-performance simulation kernels for the Synopsys VCS RTL simulator using advanced C++ techniques.
• Exploring and implementing GPU acceleration strategies with CUDA to significantly reduce simulation runtimes for customers.
• Leveraging deep knowledge of Verilog/SystemVerilog LRM to ensure accurate and reliable simulation across diverse design environments.
• Integrating AI-powered tools (such as Cursor, GitHub Copilot, and generative AI assistants) to automate code generation and debugging processes.
• Mentoring and guiding junior engineers, fostering skills development and technical growth within the team.
• Collaborating with distributed R&D teams to maintain Synopsys' leadership and drive innovation in the EDA industry.

As a senior staff engineer, you will have a significant impact on the company's success. You will be responsible for driving the evolution of the world's fastest Verilog simulator, setting new industry standards for performance and reliability. You will also empower customers to achieve greater productivity and efficiency through advanced simulation capabilities and reduced runtimes.

To be successful in this role, you will need to have:

• 8-10 years of relevant experience.
• Expert-level proficiency in C++ with proven experience in performance-critical software development.
• Deep understanding of Verilog/SystemVerilog Language Reference Manuals (LRM) and simulation methodologies.
• Hands-on experience with GPU programming, especially using CUDA for parallel acceleration.
• Familiarity with AI-powered development tools such as Cursor, GitHub Copilot, and generative AI assistants.
• Strong architectural design skills and ability to analyze and optimize complex software systems.
• Experience in mentoring and guiding junior engineers within an R&D environment.

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