Our high-speed interface IP (PCIE/CXL/USB/DP) subsystem solution is gradually becoming a key module of AI acceleration, GPGPU, Big-Data SOC chips. More and more customers have adopted our latest PCIE GEN6/GEN7 with CXL/IDE to improve security, reduce system latency, and meet the high bandwidth demands of high-end SOCs such as various cloud services, AI, and GPGPU.

Responsibilities:

• Implement IP (PCIE/CXL/USB/DP) subsystem design using synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Work with internal teams and customers to ensure successful integration and validation of the IP subsystem.
• Collaborate with cross-functional teams to develop and maintain design documentation, test plans, and other deliverables.

Requirements:

• Minimum 5+ years of experience in IP/ASIC/SOC design implementation.
• Hands-on experience in synthesis, timing optimization, SDC writing, CDC/RDC checking, etc.
• Domain understanding of one of the interface standards: PCIe, USB, Display Port, Ethernet, or DDR.
• Good communication skills while interacting with internal teams and customers.

Preferred Experience:

• Experience in Design Compiler, Fusion Compiler, PrimeTime, Spyglass, or VC Spyglass.
• Experience in DesignWare Core IPs or PHYs.
• Experience in TCL, Perl, Python, or other shell scripting.

Benefits:

• Competitive salary and benefits package.
• Opportunities for professional growth and development.
• Collaborative and dynamic work environment.

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Your primary focus will be on supporting customers in enjoing Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge. Additionally, you will be knowledgeable in multiple domains of design implementation and understand codependency of flow and methodology such as Macro & Standard Cell Placement, Clock Tree Synthesis, Routing, Advanced Timing Optimization techniques.

You will also articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

As a member of our high-performing Customer Application Services team, you will collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.

Responsibilities:

• Support customers in enjoying Synopsys products, specifically in the areas of Place & Route (physical), Synthesis (logical and physical), STA experience and knowledge.
• Articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).
• Collaborate closely with R&D, sales, and product groups to ensure that Synopsys customers achieve their design goals efficiently and effectively.
• Manage multiple customer activities concurrently, and work with Account Managers and AC management to set their priorities.
• Sales support roles include product demonstrations, evaluations, and competitive benchmarking. Customer support roles include training, problem resolution, and technical account management.

Key Qualifications:

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

Preferred Experience:

• BSEE or equivalent, required with 7+ years of experience, or MSEE, or equivalent with 5+ years of experience.
• Tool knowledge expected: Back end P&R tools (Fusion Compiler, ICC2, Innovus)
• Tool knowledge (preferred): front end Synthesis tools (Fusion Compiler, Design Compiler, Genus),
• Tool knowledge (preferred): STA (Primetime, Tempus)

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These engineers play a crucial role in advancing technology and enabling innovations in various industries.

You are a seasoned hardware engineering professional with a passion for advanced silicon package design and a proven track record in delivering innovative solutions for complex semiconductor challenges. With more than a decade of hands-on experience in package and interposer design, you possess a deep understanding of the latest advancements in 3DIC and multi-physics analysis.

Collaborating with cross-functional teams during early design stages to optimize and define SIPI (Signal Integrity/Power Integrity) performance requirements, including bump mapping and power estimation.

Designing and developing advanced silicon package solutions such as silicon interposers, RDL fanout packages, and silicon bridge packages.

Modeling and analyzing advanced package designs to ensure optimal electrical, thermal, and mechanical performance.

Representing Synopsys on business unit projects as a technical leader and subject matter expert in advanced packaging.

Resolving a wide range of design and integration issues using creative, data-driven approaches.

Supporting customer engagements in exploring and implementing advanced package solutions with Synopsys IPs.

Collaborating with global teams to share best practices and drive innovation in advanced packaging methodologies.

Empowering Synopsys and its customers to deliver next-generation, high-performance silicon solutions.

Accelerating the adoption of advanced packaging technologies that enable new levels of integration and energy efficiency.

Enhancing the performance, reliability, and manufacturability of Synopsys IP test chip packages.

Driving technical excellence and innovation in business unit projects that define Synopsys' leadership in the semiconductor industry.

Mentoring and guiding engineering peers, fostering a culture of knowledge sharing and continuous improvement.

Setting new industry standards for quality, performance, and innovation in advanced package design.

Building and strengthening customer relationships through expert support and collaboration.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products.

Job Description

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.

You Are:

You are a passionate and forward-thinking digital design expert with a strong foundation in ASIC RTL design and a proven track record of delivering complex, high-performance IP cores. With a Bachelor’s or Master’s degree in EE, EC, or VLSI and over four years of relevant industry experience, you thrive in dynamic, multi-site environments and excel at translating functional specifications into robust, scalable architectures.

Responsibilities

Architecting and implementing state-of-the-art RTL designs for the DesignWare IP family, targeting commercial, enterprise, and automotive applications.

Translating standard and functional specifications into detailed micro-architectures and comprehensive design documentation for medium to high complexity features.

Leading and contributing hands-on to RTL coding, synthesis, CDC analysis, debug, and test development tasks.

Collaborating with global teams and engaging directly with customers to understand and refine specification requirements.

Driving technical excellence in design processes, including linting, static timing analysis, formal checking, and P&R-aware synthesis using tools such as Fusion Compiler.

Mentoring and technically leading a team of designers, providing guidance on best practices and innovative design methodologies.

Utilizing version control systems and scripting to manage design flows and automate repetitive tasks for improved efficiency.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related field.

4+ years of hands-on industry experience in ASIC RTL design, with a strong portfolio of completed projects.

Deep expertise in data path and control path design, including experience with Reed Solomon FEC, BCH codes, CRC architectures, and MAC SEC engines.

Proficiency in synthesizable Verilog/SystemVerilog, simulation tools, and design flows including lint, CDC, synthesis, and static timing analysis.

Familiarity with high-speed design (>600MHz), P&R-aware synthesis, and EDA tools such as Fusion Compiler.

Experience with version control systems (e.g., Perforce) and scripting languages (Perl, Shell) for design automation.

Knowledge of industry protocols: Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA (AMBA2, AXI).

Exposure to quality processes in IP design and verification is an advantage.

Prior experience as a technical lead or mentor is highly desirable.

Who We Are Looking For

Innovative thinker with a solutions-oriented mindset and a passion for technology.

Excellent communicator who thrives in collaborative, multicultural, and multi-site environments.

Natural leader with mentoring abilities, fostering inclusion and diversity within the team.

Detail-oriented professional with strong analytical and problem-solving skills.

Self-motivated, adaptable, and eager to drive technical excellence and process improvements.

Committed to continuous learning and staying ahead of industry trends.

The Team You’ll Be A Part Of

You will join the R&D Solutions Group at our Bangalore Design Center, as part of the DesignWare IP Design team. This diverse and innovative group is dedicated to architecting, developing, and delivering cutting-edge IP cores that enable Synopsys’ global customers to achieve their design goals.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

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Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries.

Job Description

Category

Engineering

Hire Type

Employee

Job ID

16005

Remote Eligible

No

Date Posted

03/05/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished and forward-thinking engineering professional with a deep passion for the intersection of artificial intelligence and semiconductor design. Your expertise spans RTL-to-GDSII flows, and you have hands-on experience with industry-leading EDA tools, especially those driving the next generation of AI and high-performance compute silicon. You are highly analytical, able to dissect complex design challenges and architect robust, scalable solutions that address both immediate and future technology needs. You thrive in customer-facing roles, translating requirements into actionable methodologies and championing innovation every step of the way.

What You’ll Be Doing:

• Partnering with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs, and libraries.

• Creating and optimizing design flows and solutions to meet aggressive PPA (performance, power, area) targets for high-frequency cores, automotive, and high-capacity AI/compute designs.

• Enabling and deploying flows/solutions leveraging Synopsys offerings such as Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, utilizing Tcl/Python scripting for automation.

• Collaborating cross-functionally with customers, R&D, and internal teams to drive innovative solution and feature development that anticipates and addresses real-world design challenges.

• Leading and mentoring a team of junior application engineers, providing technical guidance, coaching, and project management support to ensure successful execution of deliverables.

• Delivering technical presentations, application notes, and best practices to both internal and external stakeholders, supporting knowledge-sharing and customer enablement.

The Impact You Will Have:

• Accelerate customer adoption of next-generation AI-driven design methodologies, empowering them to achieve breakthrough silicon results.

• Shape Synopsys’ technology direction by providing valuable field insights and partnering with R&D on new feature development.

• Reduce time-to-market and improve competitiveness for customers through innovative flow optimization and automation.

• Drive Synopsys’ leadership in AI-powered EDA solutions, further differentiating our offerings in a competitive market.

• Elevate the technical capabilities of the application engineering team through mentorship and cross-training.

• Enhance customer satisfaction and loyalty through proactive engagement, expert troubleshooting, and tailored technical support.

What You’ll Need:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5 + years of relevant experience.

• Deep understanding of RTL-to-GDSII flows and hands-on experience with backend P&R tools (Fusion Compiler, ICC2, or similar).

• Expertise in physical synthesis, timing closure, clock tree synthesis (CTS), and routing at advanced technology nodes.

• Proficiency in Tcl and Python scripting for automating EDA workflows and optimizing design methodologies.

• Strong technical account management skills and a proven ability to lead and mentor teams in a high-performance environment.

• Outstanding verbal and written communication, presentation, and customer interaction skills.

Who You Are:

• Collaborative and empathetic leader, skilled at building relationships and enabling the success of others.

• Analytical thinker with a problem-solving mindset and a passion for continuous improvement.

• Adaptable and resilient in the face of evolving customer requirements and technology landscapes.

• Strong organizational skills, able to manage multiple projects and priorities with poise.

• Driven by curiosity and a desire to innovate at the forefront of AI and semiconductor design.

The Team You’ll Be A Part Of:

You’ll join a dynamic and diverse Application Engineering team at Synopsys Bangalore, dedicated to driving customer success and innovation in AI-enabled design automation. The team partners closely with global customers, R&D, and product management to deliver state-of-the-art solutions for the most advanced silicon on the planet. With a culture rooted in collaboration, technical excellence, and mentorship, you’ll have the opportunity to lead, learn, and contribute to the next wave of EDA innovation.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Benefits

At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. We're proud to provide the comprehensive benefits and rewards that our team truly deserves.

Visit Benefits Page

• ### Health & Wellness

Comprehensive medical and healthcare plans that work for you and your family.

• ### Time Away

In addition to company holidays, we have ETO and FTO Programs.

• ### Family Support

Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.

• ### ESPP

Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.

• ### Retirement Plans

Save for your future with our retirement plans that vary by region and country.

• ### Compensation

Competitive salaries.

\\ Benefits vary by country and region - check with your recruiter to confirm

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What you'll do

• Design and implement SoC solutions using Synopsys EDA tools and IP.
• Advise customer design and CAD teams.

What you need

• BS/MS/PhD in relevant engineering fields.
• 7+ years in Place & Route with Fusion Compiler/ICC2.

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What you'll do

• The primary focus of the Physical Design Specialist (PDS) is to support the sale and adoption of Synopsys products to help customers achieve tangible and lasting performance improvements in the cost, quality, and development time for projects.
• In addition, PDS AEs will articulate design methodologies involving Synopsys tools at a very advanced Node (Sub 5nm) using Synopsys Full RTL-to-GDSII solution (Fusion Compiler / IC Compiler II/ICC2).

What you need

• Design Implementation experience should include ASIC design using industry-standard tools (Placement, Optimization, CTS, Routing)
• RTL to GDSII full flow experience or knowledge is preferable
• Strong interest and understanding of Advanced Node & Design methodologies are required.
• In-depth Synopsys Back end tool (Logical and Physical Synthesis, AI methodologies, Timing Closure techniques, Macro Placement, Routing at advanced Node, Static Timing Analysis, including noise analysis) experience and knowledge are required.
• Knowledge of several Clock Tree Synthesis methodologies like H-Tree, MS-CTS is preferred
• Excellent verbal and written presentation/communication skills are mandatory.
• Customer sensitivity, the ability to multiplex many issues & set priorities, and the desire to help customers exploit new technologies are essential for success in the position.

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What you'll do

• Providing expert technical guidance and engineering insight to support Synopsys product adoption and usability for leading semiconductor customers.
• Diagnosing, troubleshooting, and resolving complex technical issues during customer installations and deployments.
• Training customers on new implementations, features, and capabilities of Synopsys RTL2GDS full flow solutions.

What you need

• Extensive experience with RTL to GDSII full flow and advanced node design methodologies.
• Hands-on proficiency with synthesis, physical design, static timing analysis, equivalence checking, parasitic extraction, DRC/LVS, and power analysis.

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What you'll do

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.

What you need

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 4 to 7+ years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.

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What you'll do

• Providing technical guidance and hands-on support to customers integrating Synopsys Interface IP (PCI Express and High Speed SerDes design) into their ASIC SoC/systems
• Conducting detailed integration reviews at key customer milestones and troubleshooting complex integration challenges throughout the SoC design flow.

What you need

• Masters with 10+yrs of Industry experience or equivalent
• At least 10+ years of experience in IP design, ASIC/SoC integration, or related customer-facing engineering roles (exceptional candidates with strong silicon debug and academic background considered)

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What you'll do

• Drive global customer adoption of Synopsys Implementation products by providing expert technical guidance and support throughout the RTL-to-GDS flow.
• Diagnose and resolve synthesis and place-and-route challenges, leveraging in-depth knowledge of customer designs and Synopsys tools.

What you need

• Expertise in implementation methodologies, with deep hands-on experience in Synopsys Fusion Compiler.
• Thorough understanding of RTL-to-GDS flows and methodologies, including synthesis, place & route, and timing analysis.

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What you'll do

• Drive global customer adoption of Synopsys Implementation products by providing expert technical guidance and support throughout the RTL-to-GDS flow.
• Diagnose and resolve synthesis and place-and-route challenges, leveraging in-depth knowledge of customer designs and Synopsys tools.

What you need

• Expertise in implementation methodologies, with deep hands-on experience in Synopsys Fusion Compiler.
• Thorough understanding of RTL-to-GDS flows and methodologies, including synthesis, place & route, and timing analysis.

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What you'll do

Develop a complete front-to-back end design implementation methodology (RTL to GDSII) using Synopsys' best in class tools and technologies.

Work with leading edge designs and teams to drive the industry best PPA for IP designs.

Evaluate and exercise various aspects of the development flow which may include design for test logic, synthesis, place & route, timing and power (incl. EM/IR) optimization and analysis.

Develop and maintain best in class digital design methodologies, including documentation, scripts, and training materials.

Work as a liaison between EDAG tool and IP design teams.

Continuously improve and refine design processes to enhance efficiency and performance.

What you need

BS or MS in EE with 10+ years of hands-on experience developing high-speed digital IP cores and/or SOCs.

Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.

Direct hands-on experience with Fusion Compiler or industry equivalent Synthesis and Place & Route tools.

Ability to facilitate cross-functional collaboration, including fostering innovation, improving communication, and driving results.

Good analysis, debugging, and problem-solving skills.

Solid written and verbal communication skills and the ability to create clear and concise documentation and provide trainings.

Familiarity with other Synopsys tools (Primetime, PrimePower, RLTA, CoreTools) is a plus.

Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR is a plus.

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What you'll do

Working on Functional Verification and Design Implementation.

• Using tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools.

• Leveraging your understanding of advanced process nodes.

• Utilizing your scripting skills to automate processes.

What you need

BS with 3-5 years of direct hands-on experience.

• Proficiency in design closure.

• Experience with tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools will be added value.

• Knowledge of Python, Perl, and TCL scripting languages.

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What you'll do

Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys' industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

What you need

Bachelor's and/or Master's degree in Electrical Engineering or a related field.

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