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We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.</p>\n<p>You Are: You are a passionate and inventive analog circuit design engineer with a deep-rooted curiosity for emerging technologies and industry-leading semiconductor processes. You thrive in dynamic, collaborative environments and are recognized for your ability to balance technical depth with practical implementation.</p>\n<p>Responsibilities: Designing and developing best-in-class ESD and Latch-Up robust solutions for advanced interface IPs using cutting-edge FinFet, FDSOI, and BCD processes. Owning the full lifecycle of ESD structures, from schematic design, simulation, and layout to silicon qualification and production release. Leading and executing I/O development, including I/O ring design, review, and optimization for performance and robustness. Developing and qualifying Interface Testchips, ensuring comprehensive ESD and Latch-Up validation to meet global customer requirements. Running ESD simulations by building detailed ESD networks and performing advanced analyses to ensure design integrity. Applying foundry-provided PERC (Physical Verification Rule Check) rules and using PERC check tools to validate compliance and enhance design quality. Collaborating closely with foundry partners, design, and layout teams to ensure timely and effective integration of ESD and LU solutions.</p>\n<p>The Impact You Will Have: Elevating the reliability and performance of Synopsys&#39; interface IPs, directly influencing the success of global semiconductor customers. Driving innovation in analog circuit design for next-generation silicon technologies, helping Synopsys maintain its leadership in the industry. Reducing field failures and increasing product longevity by delivering robust ESD and Latch-Up protection solutions. Accelerating time-to-market for customer products through efficient and high-quality design practices. Fostering a culture of technical excellence and continuous improvement within the analog design team. Building strong partnerships with foundries and cross-functional teams, enhancing collaboration and knowledge sharing across projects.</p>\n<p>Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.</p>\n<p style=\"margin-top:24px;font-size:13px;color:#666;\">XML job scraping automation by <a href=\"https://yubhub.co\">YubHub</a></p>","url":"https://yubhub.co/jobs/job_fc9a9b7c-a45","directApply":true,"hiringOrganization":{"@type":"Organization","name":"Synopsys","sameAs":"https://careers.synopsys.com","logo":"https://logos.yubhub.co/careers.synopsys.com.png"},"x-apply-url":"https://careers.synopsys.com/job/noida/analog-io-design-sr-staff-engineer/44408/93647959696","x-work-arrangement":"onsite","x-experience-level":"senior","x-job-type":"full-time","x-salary-range":null,"x-skills-required":["Analog circuit design","ESD and Latch-Up robustness","FinFet, FDSOI, and BCD process technologies","PERC rules and PERC check tools","Foundry-provided PERC rules"],"x-skills-preferred":[],"datePosted":"2026-04-24T14:13:21.724Z","jobLocation":{"@type":"Place","address":{"@type":"PostalAddress","addressLocality":"Noida"}},"employmentType":"FULL_TIME","occupationalCategory":"Engineering","industry":"Technology","skills":"Analog circuit design, ESD and Latch-Up robustness, FinFet, FDSOI, and BCD process technologies, PERC rules and PERC check tools, Foundry-provided PERC rules"}]}