We are seeking a highly skilled ASIC Physical Design Staff Engineer to join our team. As a Staff Engineer, you will be responsible for implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes, ensuring world-class performance and quality. You will also drive timing closure efforts, especially above ~2GHz, and resolve complex challenges related to mixed signal and macro IP integration.

Key Responsibilities:

• Implementing and integrating DDR, HBM, and HBI IP at advanced technology nodes
• Driving timing closure efforts, especially above ~2GHz
• Resolving complex challenges related to mixed signal and macro IP integration
• Designing and optimizing clock trees with tight skew balancing to meet stringent performance requirements
• Collaborating daily with local and US counterparts, contributing to technical discussions, and sharing best practices across teams
• Leading project tasks independently, providing regular updates to management, and representing the organization in business unit and company-wide projects
• Mentoring junior engineers, guiding them through technical challenges, and fostering a culture of continuous learning and innovation

Requirements:

• Minimum 6 years of experience in ASIC physical design, preferably with post-graduate qualifications
• Expertise in tools such as Design Compiler (DC), IC Compiler II (ICC2), PrimeTime SI (PT-SI), and Formality (FC)
• Proven experience with DDR/HBM/HBI timing closure, implementation, and IP integration
• Strong analytical and problem-solving skills, with a track record of resolving complex technical issues
• Ability to independently lead project tasks, mentor junior team members, and work collaboratively

Benefits:

• Comprehensive medical and healthcare plans
• Time away from work for vacation, sick leave, and family care
• Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
• ESPP (Employee Stock Purchase Plan)
• Retirement plans
• Competitive salaries

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Applications Engineering, Staff Engineer

Seongnam-si, Gyeonggi-do, South Korea

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Hire Type EmployeeJob ID 17125Date posted 04/23/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated Staff Engagement Applications Engineer with over 6~ 8 years of hands-on experience in synthesis or formal verification for Tape out project. Your technical expertise helps customer to succeedfor most of Tape out projects to our worldwide key customers to accelerate business growth. You thrive in dynamic environments and possess excellent communication skills, including a strong command of English. Your background in EE/CS, coupled with your experience with EDA tools like DC, Formality, RTLA, and Fusion Compiler, makes you an ideal fit for this role.

What You’ll Be Doing:

• Providing front-end (Synthesis, Equivalence Check) technical support to field engineers, technicians, and product support personnel.

• Diagnosing, troubleshooting, and debugging complex electro/mechanical equipment, computer systems, and software.

• Collaborating with customers to understand their technical requirements and deliver tailored solutions.

• Conductingtraining sessions and workshops for both customers and internal teams.

• Developing andmaintainingtechnical documentation and support materials.

• Working closely with the development team toidentifyand resolve product issues.

The Impact You Will Have:

• Enhancing customer satisfaction by deliveringtimelyand effective technical support.

• Contributing to the development and enhancement of Synopsys products.

• Helping customers maximize the value of Synopsys technologies.

• Reducing downtime and increasing the efficiency of customer operations.

• Strengthening customer relationships and building trust in Synopsys.

• Driving continuous improvement in support processes and best practices.

What You’ll Need:

• Bachelor’s degree orMaster's degree in Electrical Engineering, Computer Science, or a related field.

• Solid understanding of semiconductor and software technologies.

• Minimum6~8 years of hands-on experience with tape-out project execution.

• Experience in troubleshooting and debugging complex systems.

• Experience with scripting languages likeC/C++,PerlandTcl.

• Strong understanding of ASIC design flow, VLSI, and CAD development.

• Excellent analytical and problem-solving skills.

Who You Are:

• Excellent communicator with strong interpersonal skills.

• Detail-oriented and highly organized.

• Proactive and self-motivated.

• Adaptable and able to thrive in a fast-paced environment.

• Collaborative team player with a positive attitude.

The Team You’ll Be A Part Of:

You will join a dynamic and innovative team focused on supporting and driving customer success. Our team collaborates closely with customer to drive technological advancements and provide top-tier support to our customers. We are passionate about pushing the boundaries of what's possible in chip design and software security, and we are looking for like-minded individuals to join us on this exciting journey.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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Architect, AI Solutions – Digital IP Methodology & Solutions

Sunnyvale, California, United States

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Hire Type EmployeeJob ID 17037Base Salary Range $208000-$312000Date posted 04/21/2026

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished engineer with a passion for physical design and a drive to solve complex challenges in advanced semiconductor technology. With 20+ years of hands-on experience in the complete RTL-to-GDS flow, you thrive on collaborating with customers and internal teams to deliver innovative, high-value solutions. Your expertise spans advanced nodes, synthesis, design planning, and place & route, complemented by a strong command of timing closure, power reduction methodologies, DRC rules, and formal verification. You are adept at leveraging industry-leading EDA tools such as Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, and RTLA, and you are well versed with AI/ML applications, building and deploying AI Agents.

You excel in dynamic, high-performance teams, proactively sharing knowledge and mentoring peers. Your communication skills enable you to translate technical complexities into actionable insights for both customers and colleagues. You are innovative, adaptable, and eager to stay ahead in a fast-evolving domain. Your passion for continuous learning and improvement drives you to explore new methodologies, ensuring customer success and the advancement of Synopsys’ cutting-edge tools.

Above all, you are motivated by the impact of your work on the semiconductor industry and the broader technology landscape. You are ready to be a technical leader and trusted advisor, shaping the future of physical design and pushing the boundaries of what’s possible.

What You’ll Be Doing:

• Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys’ industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

• Collaborating closely with Synopsys R&D and Product Engineering teams to influence tool development, provide feedback from the field, and drive enhancements that address real-world design challenges.

• Delivering technical presentations, workshops, and training sessions to empower customers and internal teams with best practices in synthesis, place & route, timing closure, and power optimization.

• Diagnosing and resolving complex design issues, providing expert guidance on advanced node challenges, DRC closure, ECO flows, and formal verification methodologies.

• Contributing to the productivity and growth of the Application Engineering team by sharing expertise, developing technical collateral, and mentoring junior engineers.

The Impact You Will Have:

• Accelerate customer success by ensuring smooth adoption and optimal use of Synopsys’ physical design solutions across advanced technology nodes.

• Drive innovation in EDA tool development by channeling customer feedback and real-world requirements directly to Synopsys R&D teams.

• Enhance the industry’s most advanced chip design flows, enabling customers to achieve faster time-to-market and higher quality silicon.

• Position Synopsys as a trusted partner and thought leader in physical design, strengthening long-term customer relationships and industry reputation.

• Facilitate knowledge transfer and skill development within the team, raising the overall competency and effectiveness of the Applications Engineering group.

• Contribute to Synopsys’ business growth by showcasing the value and differentiation of Synopsys tools in competitive engagements and benchmark evaluations.

What You’ll Need:

• Bachelor’s and/or Master’s degree in Electrical Engineering or a related field.

• 15+ plus years of experience with the complete RTL-to-GDS physical design flow, including advanced nodes.

• Proficiency with industry-standard EDA tools: Fusion Compiler, PrimeTime, PrimeClosure, Formality, DSO.ai, FusionAI, ICV, StarRC, RTLA, and familiarity with Innovus, Genus, Tempus, Quantus, Cerebrus.

• In-depth understanding of synthesis, design planning, place & route, timing closure, power reduction, DRC rules, static timing analysis, and ECO methodologies.

• Experience with LLMs, GPT models, and other generative AI techniques.

• Strong analytical and problem-solving skills, with the ability to diagnose and resolve complex design and tool issues.

Who You Are:

• Innovative, resourceful, and proactive in driving technical solutions and continuous improvement.

• Excellent communicator, able to clearly articulate technical concepts to diverse audiences.

• Collaborative team player who thrives in a fast-paced, cross-functional environment.

• Customer-focused mindset with a passion for delivering exceptional support and building lasting relationships.

• Effective mentor and knowledge sharer, committed to uplifting the team and advancing organizational goals.

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Responsibilities:

• Collaborate with R&D architects and customers on hardware-assisted verification products.

• Drive all aspects of the technology life cycle, from development to product sign-off and customer deployment.

• Define test strategies and methodologies to improve ease-of-use, quality of results, and interoperability with other Synopsys tools.

• Become an expert in emulation and prototyping methodologies and flows, including design, partitioning, testing, synthesis, and simulation-based verification.

• Leverage your close interaction with customers, R&D, Marketing, and Sales teams to demonstrate the differentiated emulation/verification environment.

• Adapt to recognised best practices and policies in Synopsys to become proficient in various processes involved in the Product Release Cycle.

• Work with designs from varied verticals to enable and support key ZeBu products in early-stage development.

The Impact You Will Have:

• Enhance Synopsys' emulation and prototyping solutions by driving technology development and customer deployment.

• Improve the ease-of-use, quality of results, and interoperability of Synopsys tools, contributing to overall product excellence.

• Provide expert consultation for solving complex problems, thereby increasing customer satisfaction and product adoption.

• Ensure successful execution of projects from start to completion, contributing to the timely delivery of high-quality products.

• Support the advancement of cutting-edge designs in various verticals such as HPC, AI, storage, networking, and automotive.

• Facilitate the proliferation of Synopsys' differentiated emulation/verification environment through close collaboration with multiple teams.

What You’ll Need:

• BSEE/MS with 7+ years of related experience.

• Expertise in Emulation and/or Prototyping flows, systems, and methodologies.

• Strong proficiency in Verilog, System Verilog, and VHDL.

• Understanding of verification concepts and experience with functional simulators.

• Experience with scripting languages.

• Knowledge in Simulation flows, Assertion, DPI, and Transactors.

• Complex problem-solving and debugging skills.

• Strong communication skills and the ability to interact with customers and peers.

• Knowledge in synthesis and timing analysis concepts (preferred).

• Familiarity with Synopsys solutions and tools like ZeBu, HAPS, VCS, Verdi, Proto Compiler, Synplify, DC, and Formality (preferred).

• Experience with Xilinx & Altera architecture and toolchains (preferred).

• Understanding of SW/HW debug methodologies and experience with standard SW/HW debug tools (preferred).

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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What you'll do

Working on Functional Verification and Design Implementation.

• Using tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools.

• Leveraging your understanding of advanced process nodes.

• Utilizing your scripting skills to automate processes.

What you need

BS with 3-5 years of direct hands-on experience.

• Proficiency in design closure.

• Experience with tools such as Formality, Formality-ECO, Fusion Compiler, or other EDA tools will be added value.

• Knowledge of Python, Perl, and TCL scripting languages.

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What you'll do

Engaging directly with Synopsys customers to understand their design goals, challenges, and requirements, building tailored solutions that maximize their productivity and success.

• Demonstrating the unique advantages and capabilities of Synopsys' industry-leading physical design tools, including Fusion Compiler, PrimeTime, and DSO.ai, through hands-on support and customer enablement activities.

What you need

Bachelor's and/or Master's degree in Electrical Engineering or a related field.

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